/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/
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(symbol
	(rect 16 16 136 112)
	(text "ADC0820" (rect 5 0 52 12)(font "Arial" ))
	(text "inst" (rect 8 80 25 92)(font "Arial" ))
	(port
		(pt 0 32)
		(input)
		(text "clk" (rect 0 0 14 12)(font "Arial" ))
		(text "clk" (rect 21 27 35 39)(font "Arial" ))
		(line (pt 0 32)(pt 16 32)(line_width 1))
	)
	(port
		(pt 0 48)
		(input)
		(text "D[7..0]" (rect 0 0 34 12)(font "Arial" ))
		(text "D[7..0]" (rect 21 43 55 55)(font "Arial" ))
		(line (pt 0 48)(pt 16 48)(line_width 3))
	)
	(port
		(pt 120 32)
		(output)
		(text "RD" (rect 0 0 16 12)(font "Arial" ))
		(text "RD" (rect 83 27 99 39)(font "Arial" ))
		(line (pt 120 32)(pt 104 32)(line_width 1))
	)
	(port
		(pt 120 48)
		(output)
		(text "LOCK0" (rect 0 0 35 12)(font "Arial" ))
		(text "LOCK0" (rect 64 43 99 55)(font "Arial" ))
		(line (pt 120 48)(pt 104 48)(line_width 1))
	)
	(port
		(pt 120 64)
		(output)
		(text "Q[7..0]" (rect 0 0 34 12)(font "Arial" ))
		(text "Q[7..0]" (rect 65 59 99 71)(font "Arial" ))
		(line (pt 120 64)(pt 104 64)(line_width 3))
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	(drawing
		(rectangle (rect 16 16 104 80)(line_width 1))
	)
)