{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 21 14:30:17 2008 " "Info: Processing started: Wed May 21 14:30:17 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off maxmin -c maxmin " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off maxmin -c maxmin" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "calculate.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file calculate.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 calculate-one " "Info: Found design unit 1: calculate-one" {  } { { "calculate.vhd" "" { Text "E:/Electronic Competition/maxmin/calculate.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 calculate " "Info: Found entity 1: calculate" {  } { { "calculate.vhd" "" { Text "E:/Electronic Competition/maxmin/calculate.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "change.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file change.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mypack " "Info: Found design unit 1: mypack" {  } { { "change.vhd" "" { Text "E:/Electronic Competition/maxmin/change.vhd" 6 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 mypack-body " "Info: Found design unit 2: mypack-body" {  } { { "change.vhd" "" { Text "E:/Electronic Competition/maxmin/change.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "display1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file display1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 display1-one " "Info: Found design unit 1: display1-one" {  } { { "display1.vhd" "" { Text "E:/Electronic Competition/maxmin/display1.vhd" 22 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 display1 " "Info: Found entity 1: display1" {  } { { "display1.vhd" "" { Text "E:/Electronic Competition/maxmin/display1.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ADC0820.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ADC0820.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ADC0820-one " "Info: Found design unit 1: ADC0820-one" {  } { { "ADC0820.vhd" "" { Text "E:/Electronic Competition/maxmin/ADC0820.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ADC0820 " "Info: Found entity 1: ADC0820" {  } { { "ADC0820.vhd" "" { Text "E:/Electronic Competition/maxmin/ADC0820.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "maxmin.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file maxmin.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 maxmin " "Info: Found entity 1: maxmin" {  } { { "maxmin.bdf" "" { Schematic "E:/Electronic Competition/maxmin/maxmin.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "maxmin " "Info: Elaborating entity \"maxmin\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ADC0820 ADC0820:inst " "Info: Elaborating entity \"ADC0820\" for hierarchy \"ADC0820:inst\"" {  } { { "maxmin.bdf" "inst" { Schematic "E:/Electronic Competition/maxmin/maxmin.bdf" { { 200 192 312 296 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "ADC0820.vhd(44) " "Info (10425): VHDL Case Statement information at ADC0820.vhd(44): OTHERS choice is never selected" {  } { { "ADC0820.vhd" "" { Text "E:/Electronic Competition/maxmin/ADC0820.vhd" 44 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "lock ADC0820.vhd(24) " "Warning (10631): VHDL Process Statement warning at ADC0820.vhd(24): signal or variable \"lock\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"lock\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "ADC0820.vhd" "" { Text "E:/Electronic Competition/maxmin/ADC0820.vhd" 24 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "calculate calculate:inst2 " "Info: Elaborating entity \"calculate\" for hierarchy \"calculate:inst2\"" {  } { { "maxmin.bdf" "inst2" { Schematic "E:/Electronic Competition/maxmin/maxmin.bdf" { { 184 400 576 312 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "display1 display1:inst3 " "Info: Elaborating entity \"display1\" for hierarchy \"display1:inst3\"" {  } { { "maxmin.bdf" "inst3" { Schematic "E:/Electronic Competition/maxmin/maxmin.bdf" { { 168 632 824 296 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "maxmindata display1.vhd(27) " "Info (10035): Verilog HDL or VHDL information at display1.vhd(27): object \"maxmindata\" declared but not used" {  } { { "display1.vhd" "" { Text "E:/Electronic Competition/maxmin/display1.vhd" 27 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "LOCK display1.vhd(28) " "Info (10035): Verilog HDL or VHDL information at display1.vhd(28): object \"LOCK\" declared but not used" {  } { { "display1.vhd" "" { Text "E:/Electronic Competition/maxmin/display1.vhd" 28 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clkin display1.vhd(39) " "Warning (10492): VHDL Process Statement warning at display1.vhd(39): signal \"clkin\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "display1.vhd" "" { Text "E:/Electronic Competition/maxmin/display1.vhd" 39 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "calculate:inst2\|buffmin\[7\] calculate:inst2\|buffmax\[7\] " "Info: Duplicate register \"calculate:inst2\|buffmin\[7\]\" merged to single register \"calculate:inst2\|buffmax\[7\]\"" {  } { { "calculate.vhd" "" { Text "E:/Electronic Competition/maxmin/calculate.vhd" 55 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "calculate:inst2\|buffmin\[6\] calculate:inst2\|buffmax\[6\] " "Info: Duplicate register \"calculate:inst2\|buffmin\[6\]\" merged to single register \"calculate:inst2\|buffmax\[6\]\"" {  } { { "calculate.vhd" "" { Text "E:/Electronic Competition/maxmin/calculate.vhd" 55 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "calculate:inst2\|buffmin\[5\] calculate:inst2\|buffmax\[5\] " "Info: Duplicate register \"calculate:inst2\|buffmin\[5\]\" merged to single register \"calculate:inst2\|buffmax\[5\]\"" {  } { { "calculate.vhd" "" { Text "E:/Electronic Competition/maxmin/calculate.vhd" 55 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "calculate:inst2\|buffmin\[4\] calculate:inst2\|buffmax\[4\] " "Info: Duplicate register \"calculate:inst2\|buffmin\[4\]\" merged to single register \"calculate:inst2\|buffmax\[4\]\"" {  } { { "calculate.vhd" "" { Text "E:/Electronic Competition/maxmin/calculate.vhd" 55 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "calculate:inst2\|buffmin\[3\] calculate:inst2\|buffmax\[3\] " "Info: Duplicate register \"calculate:inst2\|buffmin\[3\]\" merged to single register \"calculate:inst2\|buffmax\[3\]\"" {  } { { "calculate.vhd" "" { Text "E:/Electronic Competition/maxmin/calculate.vhd" 55 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "calculate:inst2\|buffmin\[2\] calculate:inst2\|buffmax\[2\] " "Info: Duplicate register \"calculate:inst2\|buffmin\[2\]\" merged to single register \"calculate:inst2\|buffmax\[2\]\"" {  } { { "calculate.vhd" "" { Text "E:/Electronic Competition/maxmin/calculate.vhd" 55 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "calculate:inst2\|buffmin\[1\] calculate:inst2\|buffmax\[1\] " "Info: Duplicate register \"calculate:inst2\|buffmin\[1\]\" merged to single register \"calculate:inst2\|buffmax\[1\]\"" {  } { { "calculate.vhd" "" { Text "E:/Electronic Competition/maxmin/calculate.vhd" 55 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "calculate:inst2\|buffmin\[0\] calculate:inst2\|buffmax\[0\] " "Info: Duplicate register \"calculate:inst2\|buffmin\[0\]\" merged to single register \"calculate:inst2\|buffmax\[0\]\"" {  } { { "calculate.vhd" "" { Text "E:/Electronic Competition/maxmin/calculate.vhd" 55 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "calculate:inst2\|\\maxmax:i\[31\] data_in GND " "Warning: Reduced register \"calculate:inst2\|\\maxmax:i\[31\]\" with stuck data_in port to stuck value GND" {  } {  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "calculate:inst2\|\\maxmax:i\[30\] data_in GND " "Warning: Reduced register \"calculate:inst2\|\\maxmax:i\[30\]\" with stuck data_in port to stuck value GND" {  } {  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "calculate:inst2\|\\maxmax:i\[29\] data_in GND " "Warning: Reduced register \"calculate:inst2\|\\maxmax:i\[29\]\" with stuck data_in port to stuck value GND" {  } {  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "calculate:inst2\|\\maxmax:i\[28\] data_in GND " "Warning: Reduced register \"calculate:inst2\|\\maxmax:i\[28\]\" with stuck data_in port to stuck value GND" {  } {  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "calculate:inst2\|\\maxmax:i\[27\] data_in GND " "Warning: Reduced register \"calculate:inst2\|\\maxmax:i\[27\]\" with stuck data_in port to stuck value GND" {  } {  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "calculate:inst2\|\\maxmax:i\[26\] data_in GND " "Warning: Reduced register \"calculate:inst2\|\\maxmax:i\[26\]\" with stuck data_in port to stuck value GND" {  } {  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "calculate:inst2\|\\maxmax:i\[25\] data_in GND " "Warning: Reduced register \"calculate:inst2\|\\maxmax:i\[25\]\" with stuck data_in port to stuck value GND" {  } {  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "calculate:inst2\|\\maxmax:i\[24\] data_in GND " "Warning: Reduced register \"calculate:inst2\|\\maxmax:i\[24\]\" with stuck data_in port to stuck value GND" {  } {  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "calculate:inst2\|\\maxmax:i\[23\] data_in GND " "Warning: Reduced register \"calculate:inst2\|\\maxmax:i\[23\]\" with stuck data_in port to stuck value GND" {  } {  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "calculate:inst2\|\\maxmax:i\[22\] data_in GND " "Warning: Reduced register \"calculate:inst2\|\\maxmax:i\[22\]\" with stuck data_in port to stuck value GND" {  } {  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "calculate:inst2\|\\maxmax:i\[21\] data_in GND " "Warning: Reduced register \"calculate:inst2\|\\maxmax:i\[21\]\" with stuck data_in port to stuck value GND" {  } {  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "calculate:inst2\|\\maxmax:i\[20\] data_in GND " "Warning: Reduced register \"calculate:inst2\|\\maxmax:i\[20\]\" with stuck data_in port to stuck value GND" {  } {  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}