------------------------------------------------------------------------
--  ctrl.vhd -- Controll module
------------------------------------------------------------------------
--  Author : Kovacs Laszlo - Attila 
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
--                   WebPack
------------------------------------------------------------------------
--  This module on the done signal from the epp controller 
--  starts it's operation. It reads the number of images and 
--  the number of the processes from the memory. On the image number 
--  or process number transmitted by the epp controller from 
--  the computer porgram changes the displayed image number or 
--  the process number and gives the start signal. 
--  It performs incrementation or decrementation on the image or 
--  process number or performs the process.  
------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ctrl is
    Port ( CLK    : in std_logic;
           --pushbuttons
           BTN    : in std_logic_vector(4 downto 0);
           --epp
           EBUSY  : in std_logic;
           EIMGCH : in std_logic;
           EIMGNR : in std_logic_vector(3 downto 0);
           EPRCCH : in std_logic;
           EPRCNR : in std_logic_vector(2 downto 0);
           --sram
           CRD    : out std_logic;
           CDI    : in std_logic_vector(7 downto 0);
           CADR   : out std_logic_vector(19 downto 0);
           --img
           IMGNR  : out std_logic_vector(3 downto 0);
           PRCDO  : out std_logic;
           PRCNR  : out std_logic_vector(2 downto 0);
           MAXIMG : out std_logic_vector(3 downto 0);
           MAXPRC : out std_logic_vector(2 downto 0);
           --prc
           PBUSY  : in std_logic);
end ctrl;
architecture Behavioral of ctrl is

constant ctrlSTART : std_logic_vector(2 downto 0) := "000";
constant ctrlDONE : std_logic_vector(2 downto 0) := "101";
signal ctrlst : std_logic_vector(2 downto 0) := ctrlDONE;

signal maximgnr : std_logic_vector(3 downto 0) := "0000";
signal maxprcnr : std_logic_vector(2 downto 0) := "000";
signal iIMGNR : std_logic_vector(3 downto 0) := "0000";
signal iPRCDO : std_logic := '0';
signal iPRCNR : std_logic_vector(2 downto 0) := "000";
signal prevBTN, clockBTN : std_logic_vector(4 downto 0) := "00000";

begin

    CADR <= "0000000000000000000"&ctrlst(0);
    CRD <= '1' when not (ctrlst = ctrlDONE) else '0';
    IMGNR <= iIMGNR;
    PRCNR <= iPRCNR;
    PRCDO <= iPRCDO;
    MAXIMG <= maximgnr;
    MAXPRC <= maxprcnr;

    process(CLK, EBUSY)
    begin
        if EBUSY = '1' then
            ctrlst <= ctrlSTART;
        elsif rising_edge(CLK) then
            if ctrlst /= ctrlDONE then
                ctrlst <= ctrlst + 1;
            end if;
        end if;
    end process;
    
    process(CLK)
    begin
        if rising_edge(CLK) then
            case ctrlst is
            when "010" => 
                maximgnr <= CDI(3 downto 0);
            when "011" => 
                maxprcnr <= CDI(2 downto 0);
            when others =>
            end case;
        end if;
    end process;
    
    process(CLK)
    begin
        if rising_edge(CLK) then    
            if (EPRCCH = '1' or clockBTN(0) = '1' ) and PBUSY = '0' and 
                EBUSY = '0' and iPRCNR /= "000" then
                iPRCDO <= '1';
            elsif PBUSY = '1' then
                iPRCDO <= '0';
            end if;
        end if;    
    end process;

    process(CLK)
    begin
        if rising_edge(CLK) then
            if ctrlst = "100" and iPRCNR > maxprcnr then
                iPRCNR <= "000";
            elsif EPRCCH = '1' then
                iPRCNR <= EPRCNR;
            elsif clockBTN(1) = '1' and iPRCNR > "000" then
                iPRCNR <= iPRCNR - 1;
            elsif clockBTN(2) = '1' and iPRCNR < maxprcnr then
                iPRCNR <= iPRCNR + 1;
            end if;
            if ctrlst = "100" and iIMGNR > maximgnr then
                iIMGNR <= "0000";
            elsif EIMGCH = '1' then
                iIMGNR <= EIMGNR;
            elsif clockBTN(3) = '1' and iIMGNR > "0000" then
                iIMGNR <= iIMGNR - 1;
            elsif clockBTN(4) = '1' and iIMGNR < maximgnr then
                iIMGNR <= iIMGNR + 1;
            end if;
        end if;
    end process;

    process(CLK)
    begin
        if rising_edge(CLK) then    
            clockBTN <= "00000";
            if prevBTN /= BTN then
                clockBTN <= BTN;
                prevBTN <= BTN;
            end if;
        end if;
    end process;
    
end Behavioral;