?? creg.vhd
字號:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity creg is
Port ( CLK : in std_logic;
EN : in std_logic;
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0));
end creg;
architecture Behavioral of creg is
signal iDO : std_logic_vector(7 downto 0) := "00000000";
begin
DO <= iDO;
process(CLK)
begin
if rising_edge(CLK) then
if EN = '1' then
iDO <= DI;
end if;
end if;
end process;
end Behavioral;
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