?? asd.vhd
字號:
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:39:30 01/05/06
-- Design Name:
-- Module Name: asd - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity asd is
end asd;
architecture Behavioral of asd is
begin
end Behavioral;
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