------------------------------------------------------------------------
--  cfifo.vhd -- FIFO
------------------------------------------------------------------------
--  Author : Kovacs Laszlo - Attila 
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
--                   WebPack
------------------------------------------------------------------------
-- This module is a fifo memory, using one single-port blockram.
-- It signals emptyness or fullness before it would happen with 
-- two clock cycles. 
------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;use UNISIM.vcomponents.all;
entity cfifo is
    Port ( CLK   : in std_logic;
           WR    : in std_logic;
           RD    : in std_logic;
           EMPTY : out std_logic;
           FULL  : out std_logic;
           DI    : in std_logic_vector(7 downto 0);
           DO    : out std_logic_vector(7 downto 0));
end cfifo;
architecture Behavioral of cfifo is

signal addr, rdaddr, wraddr : std_logic_vector(8 downto 0) 
:= "000000000";
signal size : std_logic_vector(8 downto 0) := "000000000";


begin
    
    process(CLK)
    begin
        if rising_edge(CLK) then
            if WR = '1' then
                wraddr <= wraddr + 1;
                size <= size + 1;
            elsif RD = '1' then
                rdaddr <= rdaddr + 1;
                size <= size - 1;
            end if;
        end if;
    end process;

    addr <= wraddr when WR = '1' else rdaddr;
    EMPTY <= '1' when size = "000000010" else '0';
    FULL <= '1' when size =  "111111100" else '0';

   RAMB4_S8_inst : RAMB4_S8   generic map (      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000")   port map (      DO => DO,          ADDR => addr,      CLK => CLK,        DI => DI,          EN => '1',          RST => '0',        WE => WR
      ); 

end Behavioral;