-- Constant (K) Coded Programmable State Machine for Spartan-II and Virtex-E Devices
--
-- Version : 1.00c
-- Version Date : 14th August 2002
--
-- Start of design entry : 2nd July 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002.   This code may be contain portions patented by other 
-- third parites.  By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard 
-- is free from any claims of infringement by any third party.  Xilinx expressly 
-- disclaims any warranty with respect to the adequacy of the implementation, including 
-- but not limited to any warranty or representation that the implementation is free 
-- from claims of any third party.  Futhermore, Xilinx is providing this core as a 
-- courtesy to you and suggests that you contact all third parties to obtain the 
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- This file contains the definition of KCPSM and all the submodules which it 
-- required. The definition of KCPSM is placed at the end of this file as the order 
-- in which each entity is read is important for some simulation and synthesis tools.
-- Hence the first entity to be seen below is that of a submodule.
--
--
-- The submodules define the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the implementation. 
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
-- It is only specified in sub modules which contain primitive components.
-- 
-- library unisim;
-- use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Description of sub-modules and further low level modules.
--
------------------------------------------------------------------------------------
--
-- Definition of an 8-bit bus 4 to 1 multiplexer with embeded select signal decoding.
-- 
-- sel1  sel0a  sel0b   Y_bus 
--  
--  0      0      x     D0_bus
--  0      1      x     D1_bus
--  1      x      0     D2_bus
--  1      x      1     D3_bus
--
-- sel1 is the pipelined decode of instruction12, instruction13, and instruction15.
-- sel0a is code2 after pipeline delay.
-- sel0b is instruction14 after pipeline delay.
--
-- Requires 17 LUTs and 3 flip-flops.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity data_bus_mux4 is
    Port (         D3_bus : in std_logic_vector(7 downto 0);
                   D2_bus : in std_logic_vector(7 downto 0);    
                   D1_bus : in std_logic_vector(7 downto 0);
                   D0_bus : in std_logic_vector(7 downto 0);
            instruction15 : in std_logic;
            instruction14 : in std_logic;
            instruction13 : in std_logic;
            instruction12 : in std_logic;
                    code2 : in std_logic;
                    Y_bus : out std_logic_vector(7 downto 0);
                      clk : in std_logic );
    end data_bus_mux4;
--
architecture low_level_definition of data_bus_mux4 is
--
-- Internal signals
--
signal upper_selection : std_logic_vector(7 downto 0);
signal lower_selection : std_logic_vector(7 downto 0);
signal decode_sel1     : std_logic;
signal sel1            : std_logic;
signal sel0a           : std_logic;
signal sel0b           : std_logic;
--
-- Attribute to define LUT contents during implementation 
-- The information is repeated in the generic map for functional simulation
attribute INIT : string; 
attribute INIT of decode_lut : label is "E0";
--
begin

  -- Forming decode signals

  decode_lut: LUT3
  --translate_off
    generic map (INIT => X"E0")
  --translate_on
  port map( I0 => instruction12,
            I1 => instruction13,
            I2 => instruction15,
             O => decode_sel1 );

  sel1_pipe: FD
  port map ( D => decode_sel1,
             Q => sel1,
             C => clk);

  sel0a_pipe: FD
  port map ( D => code2,
             Q => sel0a,
             C => clk);

  sel0b_pipe: FD
  port map ( D => instruction14,
             Q => sel0b,
             C => clk);

  bus_width_loop: for i in 0 to 7 generate
  --
  -- Attribute to define LUT contents during implementation 
  -- The information is repeated in the generic map for functional simulation
  attribute INIT : string; 
  attribute INIT of high_mux_lut : label is "E4";
  attribute INIT of low_mux_lut  : label is "E4";
 
  --
  begin

    high_mux_lut: LUT3
    --translate_off
      generic map (INIT => X"E4")
    --translate_on
    port map( I0 => sel0b,
              I1 => D2_bus(i),
              I2 => D3_bus(i),
               O => upper_selection(i) );

    low_mux_lut: LUT3
    --translate_off
      generic map (INIT => X"E4")
    --translate_on
    port map( I0 => sel0a,
              I1 => D0_bus(i),
              I2 => D1_bus(i),
               O => lower_selection(i) );

    final_mux: MUXF5
    port map(  I1 => upper_selection(i),
               I0 => lower_selection(i),
                S => sel1,
                O => Y_bus(i) );

  end generate bus_width_loop;
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of an 8-bit shift/rotate process
--	
-- This function uses 11 LUTs.
-- The function contains an output pipeline register using 9 FDs.
--
-- Operation
--
-- The input operand is shifted by one bit left or right.
-- The bit which falls out of the end is passed to the carry_out.
-- The bit shifted in is determined by the select bits
--
--     code1    code0         Bit injected
--
--       0        0          carry_in           
--       0        1          msb of input_operand 
--       1        0          lsb of operand 
--       1        1          inject_bit 
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity shift_rotate_process is
    Port    (    operand : in std_logic_vector(7 downto 0);
                carry_in : in std_logic;
              inject_bit : in std_logic;
             shift_right : in std_logic;
                   code1 : in std_logic;
                   code0 : in std_logic;
                       Y : out std_logic_vector(7 downto 0);
               carry_out : out std_logic;
                     clk : in std_logic);
    end shift_rotate_process;
--
architecture low_level_definition of shift_rotate_process is
--
-- Attribute to define LUT contents during implementation 
-- The information is repeated in the generic map for functional simulation
attribute INIT : string; 
attribute INIT of high_mux_lut       : label is "E4";
attribute INIT of low_mux_lut        : label is "E4";
attribute INIT of carry_out_mux_lut  : label is "E4";
--
-- Internal signals
--
signal upper_selection : std_logic;
signal lower_selection : std_logic;
signal mux_output      : std_logic_vector(7 downto 0);
signal shift_in_bit    : std_logic;
signal carry_bit       : std_logic;
--
begin
  --
  -- 4 to 1 mux selection of the bit to be shifted in
  --

    high_mux_lut: LUT3
    --translate_off
      generic map (INIT => X"E4")
    --translate_on
    port map( I0 => code0,
              I1 => operand(0),
              I2 => inject_bit,
               O => upper_selection );

    low_mux_lut: LUT3
    --translate_off
      generic map (INIT => X"E4")
    --translate_on
    port map( I0 => code0,
              I1 => carry_in,
              I2 => operand(7),
               O => lower_selection );

    final_mux: MUXF5
    port map(  I1 => upper_selection,
               I0 => lower_selection,
                S => code1,
                O => shift_in_bit );

  --
  -- shift left or right of operand
  --
  bus_width_loop: for i in 0 to 7 generate
  --
  begin

     lsb_shift: if i=0 generate
        --
        -- Attribute to define LUT contents during implementation 
        -- The information is repeated in the generic map for functional simulation
        attribute INIT : string; 
        attribute INIT of mux_lut : label is "E4";
        --
        begin

          mux_lut: LUT3
          --translate_off
            generic map (INIT => X"E4")
          --translate_on
          port map( I0 => shift_right,
                    I1 => shift_in_bit,
                    I2 => operand(i+1),
                     O => mux_output(i) );
					   
        end generate lsb_shift;

     mid_shift: if i>0 and i<7 generate
        --
        -- Attribute to define LUT contents during implementation 
        -- The information is repeated in the generic map for functional simulation
        attribute INIT : string; 
        attribute INIT of mux_lut : label is "E4";
        --
        begin

          mux_lut: LUT3
          --translate_off
            generic map (INIT => X"E4")
          --translate_on
          port map( I0 => shift_right,
                    I1 => operand(i-1),
                    I2 => operand(i+1),
                     O => mux_output(i) );
					   
	  end generate mid_shift;

     msb_shift: if i=7 generate
        --
        -- Attribute to define LUT contents during implementation 
        -- The information is repeated in the generic map for functional simulation
        attribute INIT : string; 
        attribute INIT of mux_lut : label is "E4";
        --
        begin

          mux_lut: LUT3
          --translate_off
            generic map (INIT => X"E4")
          --translate_on
          port map( I0 => shift_right,
                    I1 => operand(i-1),
                    I2 => shift_in_bit,
                     O => mux_output(i) );
					   
	  end generate msb_shift;

     pipeline_bit: FD
     port map ( D => mux_output(i),
                Q => Y(i),
                C => clk);

  end generate bus_width_loop;
  --
  -- Selection of carry output
  --

  carry_out_mux_lut: LUT3
  --translate_off
    generic map (INIT => X"E4")
  --translate_on
  port map( I0 => shift_right,
            I1 => operand(7),
            I2 => operand(0),
             O => carry_bit );
					   
  pipeline_bit: FD
  port map ( D => carry_bit,
             Q => carry_out,
             C => clk);
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of an 8-bit logical processing unit
--	
-- This function uses 8 LUTs (4 slices) to provide the logical bit operations.
-- The function contains an output pipeline register using 8 FDs.
--
--     Code1    Code0       Bit Operation
--
--       0        0            LOAD      Y <= second_operand 
--       0        1            AND       Y <= first_operand and second_operand
--       1        0            OR        Y <= first_operand or second_operand 
--       1        1            XOR       Y <= first_operand xor second_operand
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity logical_bus_processing is
    Port (  first_operand : in std_logic_vector(7 downto 0);
           second_operand : in std_logic_vector(7 downto 0);
                    code1 : in std_logic;
                    code0 : in std_logic;
                        Y : out std_logic_vector(7 downto 0);
                      clk : in std_logic);
    end logical_bus_processing;
--
architecture low_level_definition of logical_bus_processing is
--
-- Internal signals
--
signal combinatorial_logical_processing : std_logic_vector(7 downto 0);
--
begin
 
  bus_width_loop: for i in 0 to 7 generate
  --
  -- Attribute to define LUT contents during implementation 
  -- The information is repeated in the generic map for functional simulation
  attribute INIT : string; 
  attribute INIT of logical_lut : label is "6E8A"; 
  --
  begin

     logical_lut: LUT4
     --translate_off
     generic map (INIT => X"6E8A")
     --translate_on
     port map( I0 => second_operand(i),
               I1 => first_operand(i),
               I2 => code0,
               I3 => code1,
                O => combinatorial_logical_processing(i));

     pipeline_bit: FD
     port map ( D => combinatorial_logical_processing(i),
                Q => Y(i),
                C => clk);

  end generate bus_width_loop;
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
--
-- Definition of an 8-bit arithmetic process