?? kcpsm.vhd
字號:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity program_counter is
Port ( instruction15 : in std_logic;
instruction14 : in std_logic;
instruction13 : in std_logic;
instruction12 : in std_logic;
instruction11 : in std_logic;
instruction10 : in std_logic;
instruction8 : in std_logic;
instruction7 : in std_logic;
instruction6 : in std_logic;
constant_value : in std_logic_vector(7 downto 0);
stack_value : in std_logic_vector(7 downto 0);
T_state : in std_logic;
active_interrupt : in std_logic;
carry_flag : in std_logic;
zero_flag : in std_logic;
reset : in std_logic;
flag_condition_met : out std_logic;
program_count : out std_logic_vector(7 downto 0);
clk : in std_logic);
end program_counter;
--
architecture low_level_definition of program_counter is
--
-- Internal signals
--
signal decode_a : std_logic;
signal decode_a_carry : std_logic;
signal decode_b : std_logic;
signal move_group : std_logic;
signal condition_met_internal : std_logic;
signal normal_count : std_logic;
signal increment_load_value : std_logic;
signal not_enable : std_logic;
signal selected_load_value : std_logic_vector(7 downto 0);
signal inc_load_value_carry : std_logic_vector(6 downto 0);
signal inc_load_value : std_logic_vector(7 downto 0);
signal selected_count_value : std_logic_vector(7 downto 0);
signal inc_count_value_carry : std_logic_vector(6 downto 0);
signal inc_count_value : std_logic_vector(7 downto 0);
signal count_value : std_logic_vector(7 downto 0);
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of decode_a_lut : label is "E";
attribute INIT of decode_b_lut : label is "10";
attribute INIT of condition_lut : label is "5A3C";
attribute INIT of count_lut : label is "2F";
attribute INIT of increment_lut : label is "1";
--
begin
--
-- decode instructions
--
condition_lut: LUT4
--translate_off
generic map (INIT => X"5A3C")
--translate_on
port map( I0 => carry_flag,
I1 => zero_flag,
I2 => instruction10,
I3 => instruction11,
O => condition_met_internal );
flag_condition_met <= condition_met_internal;
decode_a_lut: LUT2
--translate_off
generic map (INIT => X"E")
--translate_on
port map( I0 => instruction7,
I1 => instruction8,
O => decode_a );
decode_b_lut: LUT3
--translate_off
generic map (INIT => X"10")
--translate_on
port map( I0 => instruction13,
I1 => instruction14,
I2 => instruction15,
O => decode_b );
decode_a_muxcy: MUXCY
port map( DI => '0',
CI => '1',
S => decode_a,
O => decode_a_carry );
decode_b_cymux: MUXCY
port map( DI => '0',
CI => decode_a_carry,
S => decode_b,
O => move_group );
count_lut: LUT3
--translate_off
generic map (INIT => X"2F")
--translate_on
port map( I0 => instruction12,
I1 => condition_met_internal,
I2 => move_group,
O => normal_count );
increment_lut: LUT2
--translate_off
generic map (INIT => X"1")
--translate_on
port map( I0 => instruction6,
I1 => instruction8,
O => increment_load_value );
-- Dual loadable counter with increment on load vector
invert_enable: INV -- Inverter should be implemented in the CE to flip flops
port map( I => T_state,
O => not_enable);
count_width_loop: for i in 0 to 7 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of value_select_mux : label is "E4";
attribute INIT of count_select_mux : label is "E4";
--
begin
value_select_mux: LUT3
--translate_off
generic map (INIT => X"E4")
--translate_on
port map( I0 => instruction8,
I1 => stack_value(i),
I2 => constant_value(i),
O => selected_load_value(i) );
count_select_mux: LUT3
--translate_off
generic map (INIT => X"E4")
--translate_on
port map( I0 => normal_count,
I1 => inc_load_value(i),
I2 => count_value(i),
O => selected_count_value(i) );
register_bit: FDRSE
port map ( D => inc_count_value(i),
Q => count_value(i),
R => reset,
S => active_interrupt,
CE => not_enable,
C => clk);
lsb_carry: if i=0 generate
begin
load_inc_carry: MUXCY
port map( DI => '0',
CI => increment_load_value,
S => selected_load_value(i),
O => inc_load_value_carry(i));
load_inc_xor: XORCY
port map( LI => selected_load_value(i),
CI => increment_load_value,
O => inc_load_value(i));
count_inc_carry: MUXCY
port map( DI => '0',
CI => normal_count,
S => selected_count_value(i),
O => inc_count_value_carry(i));
count_inc_xor: XORCY
port map( LI => selected_count_value(i),
CI => normal_count,
O => inc_count_value(i));
end generate lsb_carry;
mid_carry: if i>0 and i<7 generate
begin
load_inc_carry: MUXCY
port map( DI => '0',
CI => inc_load_value_carry(i-1),
S => selected_load_value(i),
O => inc_load_value_carry(i));
load_inc_xor: XORCY
port map( LI => selected_load_value(i),
CI => inc_load_value_carry(i-1),
O => inc_load_value(i));
count_inc_carry: MUXCY
port map( DI => '0',
CI => inc_count_value_carry(i-1),
S => selected_count_value(i),
O => inc_count_value_carry(i));
count_inc_xor: XORCY
port map( LI => selected_count_value(i),
CI => inc_count_value_carry(i-1),
O => inc_count_value(i));
end generate mid_carry;
msb_carry: if i=7 generate
begin
load_inc_xor: XORCY
port map( LI => selected_load_value(i),
CI => inc_load_value_carry(i-1),
O => inc_load_value(i));
count_inc_xor: XORCY
port map( LI => selected_count_value(i),
CI => inc_count_value_carry(i-1),
O => inc_count_value(i));
end generate msb_carry;
end generate count_width_loop;
program_count <= count_value;
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
------------------------------------------------------------------------------------
--
-- Main Entity for KCPSM
--
entity kcpsm is
Port ( address : out std_logic_vector(7 downto 0);
instruction : in std_logic_vector(15 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
reset : in std_logic;
clk : in std_logic);
end kcpsm;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for KCPSM
--
architecture macro_level_definition of kcpsm is
--
------------------------------------------------------------------------------------
--
-- Components used in KCPSM and defined in subsequent entities.
--
------------------------------------------------------------------------------------
component data_bus_mux4
Port ( D3_bus : in std_logic_vector(7 downto 0);
D2_bus : in std_logic_vector(7 downto 0);
D1_bus : in std_logic_vector(7 downto 0);
D0_bus : in std_logic_vector(7 downto 0);
instruction15 : in std_logic;
instruction14 : in std_logic;
instruction13 : in std_logic;
instruction12 : in std_logic;
code2 : in std_logic;
Y_bus : out std_logic_vector(7 downto 0);
clk : in std_logic );
end component;
component shift_rotate_process
Port ( operand : in std_logic_vector(7 downto 0);
carry_in : in std_logic;
inject_bit : in std_logic;
shift_right : in std_logic;
code1 : in std_logic;
code0 : in std_logic;
Y : out std_logic_vector(7 downto 0);
carry_out : out std_logic;
clk : in std_logic);
end component;
component logical_bus_processing
Port ( first_operand : in std_logic_vector(7 downto 0);
second_operand : in std_logic_vector(7 downto 0);
code1 : in std_logic;
code0 : in std_logic;
Y : out std_logic_vector(7 downto 0);
clk : in std_logic);
end component;
component arithmetic_process
Port ( first_operand : in std_logic_vector(7 downto 0);
second_operand : in std_logic_vector(7 downto 0);
carry_in : in std_logic;
code1 : in std_logic;
code0 : in std_logic;
Y : out std_logic_vector(7 downto 0);
carry_out : out std_logic;
clk : in std_logic);
end component;
component flag_logic
Port ( data : in std_logic_vector(7 downto 0);
instruction15 : in std_logic;
instruction14 : in std_logic;
instruction13 : in std_logic;
instruction12 : in std_logic;
instruction8 : in std_logic;
instruction6 : in std_logic;
code : in std_logic_vector(2 downto 0);
shadow_zero : in std_logic;
shadow_carry : in std_logic;
shift_rotate_carry : in std_logic;
add_sub_carry : in std_logic;
reset : in std_logic;
T_state : in std_logic;
zero_flag : out std_logic;
carry_flag : out std_logic;
clk : in std_logic);
end component;
component data_bus_mux2
Port ( D1_bus : in std_logic_vector(7 downto 0);
D0_bus : in std_logic_vector(7 downto 0);
instruction15 : in std_logic;
instruction14 : in std_logic;
instruction13 : in std_logic;
instruction12 : in std_logic;
Y_bus : out std_logic_vector(7 downto 0));
end component;
component ALU_control_mux2
Port ( D1_bus : in std_logic_vector(2 downto 0);
D0_bus : in std_logic_vector(2 downto 0);
instruction15 : in std_logic;
Y_bus : out std_logic_vector(2 downto 0));
end component;
component data_register_bank
Port ( address_A : in std_logic_vector(3 downto 0);
Din_A_bus : in std_logic_vector(7 downto 0);
Dout_A_bus : out std_logic_vector(7 downto 0);
address_B : in std_logic_vector(3 downto 0);
Dout_B_bus : out std_logic_vector(7 downto 0);
instruction15 : in std_logic;
instruction14 : in std_logic;
instruction13 : in std_logic;
active_interrupt : in std_logic;
T_state : in std_logic;
clk : in std_logic);
end component;
component T_state_and_Reset
Port ( reset_input : in std_logic;
internal_reset : out std_logic;
T_state : out std_logic;
clk : in std_logic);
end component;
component interrupt_logic
Port ( interrupt : in std_logic;
instruction15 : in std_logic;
instruction14 : in std_logic;
instruction13 : in std_logic;
instruction8 : in std_logic;
instruction5 : in std_logic;
instruction4 : in std_logic;
zero_flag : in std_logic;
carry_flag : in std_logic;
shadow_zero : out std_logic;
shadow_carry : out std_logic;
active_interrupt : out std_logic;
reset : in std_logic;
T_state : in std_logic;
clk : in std_logic);
end component;
component IO_strobe_logic
Port ( instruction15 : in std_logic;
instruction14 : in std_logic;
instruction13 : in std_logic;
active_interrupt : in std_logic;
T_state : in std_logic;
reset : in std_logic;
write_strobe : out std_logic;
read_strobe : out std_logic;
clk : in std_logic);
end component;
component stack_ram
Port ( Din : in std_logic_vector(7 downto 0);
Dout : out std_logic_vector(7 downto 0);
addr : in std_logic_vector(3 downto 0);
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