library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
------------------------
entity alu181 is
port(
     s:in std_logic_VECTOR(3 downto 0);
     a,b: in std_logic_vector(7 downto 0);
     f: out std_logic_vector(7 downto 0);
     cout: out std_logic_vector(3 downto 0);
     m,cn:in std_logic;
     co,fz:out std_logic);
end alu181;
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architecture behav of alu181 is
signal A9,b9,f9:std_logic_vector(8 downto 0);
begin
a9<='0'&a;
b9<='0'&b;
process(m,cn,a9,b9)
begin
case s is
when"0000"=>if m='0' then f9<=a9+cn;
else f9<=not a9;
end if;
when"0001"=>if m='0' then f9<=(a9 or b9)+cn; else f9<=not(a9 or b9);
     end if;
when"0010"=>if m='0' then f9<=(a9 or(not b9))+cn;
     else f9<=(not a9)and b9;end if;
when"0011"=>if m='0' then f9<="000000000"-cn;else f9<="000000000";end if;
when"0100"=>if m='0' then f9<=a9+(a9 and not b9)+cn;
      else f9<=not(a9 and b9);end if;
when"0101"=>if m='0' then f9<=(a9 or b9)+(a9 and not b9)+cn;else f9<=not b9;end if;
when"0110"=>if m='0' then f9<=a9-b9-cn;else f9<=a9 xor b9;end if;
when"0111"=>if m='0' then f9<=(a9 and (not b9))-cn;
       else f9<=a9 and (not b9);end if;
when"1000"=>if m='0' then f9<=a9+(a9 and b9)+cn;else f9<=(not a9)or b9;end if;
when"1001"=>if m='0' then f9<=a9+b9+cn;else f9<=not(a9 xor b9);end if;
when"1010"=>if m='0' then f9<=(a9 or (not b9))+(a9 and b9)+cn;else f9<=b9;end if;
when"1011"=>if m='0' then f9<=(a9 and b9)-cn;else f9<=a9 and b9;end if;
when"1100"=>if m='0' then f9<=a9+a9+cn;else f9<="000000001";end if;
when"1101"=>if m='0' then f9<=(a9 or b9)+a9+cn;else f9<=a9 or(not b9);end if;
when"1110"=>if m='0' then f9<=(a9 or(not b9))+a9+cn;else f9<=a9 or b9;end if;
when"1111"=>if m='0' then f9<=a9-cn;else f9<=a9;end if;
when others =>f9<="000000000";
end case;
If(a9=b9)then fz<='0';end if;
end process;
f<=f9(7 downto 0);co<=f9(8);
cout<="0000"when f9(8)='0' else "0001";
end behav;