library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity majority is
port(	clk,resetn:	in	std_logic;
		d_in:		in 	std_logic_vector(3 downto 0);
		d_filtr:	out	std_logic_vector(3 downto 0));
end majority;
architecture a of majority is
type array_4 is array (3 downto 0) of std_logic_vector(2 downto 0);
signal shift_data:array_4;
signal d_filtr_i:std_logic_vector(3 downto 0);
begin
p1:process(clk,resetn)
begin
	if resetn='0' then
		for i in 0 to 3 loop
			shift_data(i)<=(others =>'0');
		end loop;
	elsif rising_edge(clk) then
		for i in 0 to 3 loop
			shift_data(i) <=shl(shift_data(i),"1");
			shift_data(i)(0) <= d_in(i);
		end loop;
	end if;
end process p1;
p2:process(shift_data)
type array_42 is array(3 downto 0) of std_logic_vector(1 downto 0);
variable count :array_42;
begin
	for i in 0 to 3 loop
		count(i) := shift_data(i)(2)+('0'&shift_data(i)(1))+('0'&shift_data(i)(0));
		if count(i) >= 2 then
			d_filtr_i(i)<='1';
		else 
			d_filtr_i(i)<='0';
		end if;
	end loop;
end process p2;
p3:process(clk,resetn)
begin
	if resetn='0' then
		d_filtr<=(others=>'0');
	elsif rising_edge(clk) then
		d_filtr<= d_filtr_i;
	end if;
end process p3;
end a;