; N/A   ; None         ; 13.014 ns  ; \counter:Q[6]        ; SEGOUT[1]   ; CLK_4M     ;
; N/A   ; None         ; 13.003 ns  ; \counter:Q[6]        ; SEGOUT[0]   ; CLK_4M     ;
; N/A   ; None         ; 12.825 ns  ; \counter:Q[5]        ; SELOUT[1]   ; CLK_4M     ;
; N/A   ; None         ; 12.660 ns  ; \counter:Q[5]        ; SEGOUT[1]   ; CLK_4M     ;
; N/A   ; None         ; 12.651 ns  ; \counter:Q[5]        ; SEGOUT[0]   ; CLK_4M     ;
; N/A   ; None         ; 12.584 ns  ; \counter:Q[4]        ; SEGOUT[6]   ; CLK_4M     ;
; N/A   ; None         ; 12.356 ns  ; \counter:Q[4]        ; SEGOUT[1]   ; CLK_4M     ;
; N/A   ; None         ; 12.345 ns  ; \counter:Q[4]        ; SEGOUT[0]   ; CLK_4M     ;
; N/A   ; None         ; 11.848 ns  ; \counter:Q[6]        ; SELOUT[2]   ; CLK_4M     ;
; N/A   ; None         ; 9.792 ns   ; \counter:Q[4]        ; SELOUT[0]   ; CLK_4M     ;
+-------+--------------+------------+----------------------+-------------+------------+


+-----------------------------------------------------------------------------------------------------+
; th                                                                                                  ;
+---------------+-------------+-----------+--------+---------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To                                    ; To Clock ;
+---------------+-------------+-----------+--------+---------------------------------------+----------+
; N/A           ; None        ; 0.573 ns  ; KEY[3] ; DEBOUNCING:\debounuing:U4|\debunce:d0 ; CLK_4M   ;
; N/A           ; None        ; 0.402 ns  ; KEY[2] ; DEBOUNCING:\debounuing:U3|\debunce:d0 ; CLK_4M   ;
; N/A           ; None        ; 0.146 ns  ; KEY[0] ; DEBOUNCING:\debounuing:U1|\debunce:d0 ; CLK_4M   ;
; N/A           ; None        ; 0.134 ns  ; KEY[1] ; DEBOUNCING:\debounuing:U2|\debunce:d0 ; CLK_4M   ;
; N/A           ; None        ; -3.466 ns ; clr    ; DEBOUNCING:\debounuing:U3|\debunce:r  ; CLK_4M   ;
; N/A           ; None        ; -3.466 ns ; clr    ; DEBOUNCING:\debounuing:U1|\debunce:r  ; CLK_4M   ;
; N/A           ; None        ; -3.466 ns ; clr    ; DEBOUNCING:\debounuing:U1|\debunce:s  ; CLK_4M   ;
; N/A           ; None        ; -3.466 ns ; clr    ; DEBOUNCING:\debounuing:U3|\debunce:d1 ; CLK_4M   ;
; N/A           ; None        ; -3.466 ns ; clr    ; DEBOUNCING:\debounuing:U1|\debunce:d1 ; CLK_4M   ;
; N/A           ; None        ; -3.466 ns ; clr    ; DEBOUNCING:\debounuing:U1|\debunce:d0 ; CLK_4M   ;
; N/A           ; None        ; -3.479 ns ; clr    ; DEBOUNCING:\debounuing:U3|\debunce:s  ; CLK_4M   ;
; N/A           ; None        ; -3.479 ns ; clr    ; DEBOUNCING:\debounuing:U4|\debunce:s  ; CLK_4M   ;
; N/A           ; None        ; -3.479 ns ; clr    ; DEBOUNCING:\debounuing:U4|\debunce:r  ; CLK_4M   ;
; N/A           ; None        ; -3.479 ns ; clr    ; DEBOUNCING:\debounuing:U2|\debunce:s  ; CLK_4M   ;
; N/A           ; None        ; -3.479 ns ; clr    ; DEBOUNCING:\debounuing:U2|\debunce:r  ; CLK_4M   ;
; N/A           ; None        ; -3.479 ns ; clr    ; DEBOUNCING:\debounuing:U2|\debunce:d0 ; CLK_4M   ;
; N/A           ; None        ; -3.479 ns ; clr    ; DEBOUNCING:\debounuing:U2|\debunce:d1 ; CLK_4M   ;
; N/A           ; None        ; -3.479 ns ; clr    ; DEBOUNCING:\debounuing:U4|\debunce:d0 ; CLK_4M   ;
; N/A           ; None        ; -3.479 ns ; clr    ; DEBOUNCING:\debounuing:U4|\debunce:d1 ; CLK_4M   ;
; N/A           ; None        ; -3.479 ns ; clr    ; DEBOUNCING:\debounuing:U3|\debunce:d0 ; CLK_4M   ;
+---------------+-------------+-----------+--------+---------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Wed Jun 28 15:17:05 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off keys_test -c keys_test --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK_4M" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "\counter:Q[0]" as buffer
    Info: Detected ripple clock "\counter:Q[2]" as buffer
Info: Clock "CLK_4M" has Internal fmax of 185.01 MHz between source register "DEBOUNCING:\debounuing:U1|dly" and destination register "\key_decoder:ZOUT[0]" (period= 5.405 ns)
    Info: + Longest register to register delay is 5.423 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y20_N1; Fanout = 12; REG Node = 'DEBOUNCING:\debounuing:U1|dly'
        Info: 2: + IC(1.241 ns) + CELL(0.590 ns) = 1.831 ns; Loc. = LC_X24_Y20_N7; Fanout = 3; COMB Node = 'Mux~2083'
        Info: 3: + IC(0.780 ns) + CELL(0.292 ns) = 2.903 ns; Loc. = LC_X23_Y20_N2; Fanout = 1; COMB Node = 'Mux~2084'
        Info: 4: + IC(1.913 ns) + CELL(0.607 ns) = 5.423 ns; Loc. = LC_X16_Y17_N8; Fanout = 2; REG Node = '\key_decoder:ZOUT[0]'
        Info: Total cell delay = 1.489 ns ( 27.46 % )
        Info: Total interconnect delay = 3.934 ns ( 72.54 % )
    Info: - Smallest clock skew is 0.279 ns
        Info: + Shortest clock path from clock "CLK_4M" to destination register is 9.268 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 7; CLK Node = 'CLK_4M'
            Info: 2: + IC(1.065 ns) + CELL(0.935 ns) = 3.469 ns; Loc. = LC_X16_Y17_N3; Fanout = 8; REG Node = '\counter:Q[2]'
            Info: 3: + IC(5.088 ns) + CELL(0.711 ns) = 9.268 ns; Loc. = LC_X16_Y17_N8; Fanout = 2; REG Node = '\key_decoder:ZOUT[0]'
            Info: Total cell delay = 3.115 ns ( 33.61 % )
            Info: Total interconnect delay = 6.153 ns ( 66.39 % )
        Info: - Longest clock path from clock "CLK_4M" to source register is 8.989 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 7; CLK Node = 'CLK_4M'
            Info: 2: + IC(1.065 ns) + CELL(0.935 ns) = 3.469 ns; Loc. = LC_X16_Y17_N1; Fanout = 29; REG Node = '\counter:Q[0]'
            Info: 3: + IC(4.809 ns) + CELL(0.711 ns) = 8.989 ns; Loc. = LC_X25_Y20_N1; Fanout = 12; REG Node = 'DEBOUNCING:\debounuing:U1|dly'
            Info: Total cell delay = 3.115 ns ( 34.65 % )
            Info: Total interconnect delay = 5.874 ns ( 65.35 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Warning: Circuit may not operate. Detected 13 non-operational path(s) clocked by clock "CLK_4M" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "\counter:Q[4]" and destination pin or register "\key_decoder:ZOUT[0]" for clock "CLK_4M" (Hold time is 3.113 ns)
    Info: + Largest clock skew is 6.023 ns
        Info: + Longest clock path from clock "CLK_4M" to destination register is 9.268 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 7; CLK Node = 'CLK_4M'
            Info: 2: + IC(1.065 ns) + CELL(0.935 ns) = 3.469 ns; Loc. = LC_X16_Y17_N3; Fanout = 8; REG Node = '\counter:Q[2]'
            Info: 3: + IC(5.088 ns) + CELL(0.711 ns) = 9.268 ns; Loc. = LC_X16_Y1