?? control.vhd.bak
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--本程序用于711所智能CAN網卡
--此程序負責控制第一、二路CAN通道
--作者：JYH
--設計開始時間：2003年8月4日
--設計完成時間：
--版本號:1.0
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity control is
port
(jp : in std_logic_vector(7 downto 0); --跨接針
--************************************************************************ --本段定義單片機端口引腳
p0a, p0b : inout std_logic_vector(7 downto 0);
p2a, p2b : in std_logic_vector(7 downto 0);
alea, aleb : in std_logic;
wra, wrb : in std_logic;
rda, rdb : in std_logic;
c51rsta, c51rstb : out std_logic;
sjarsta, sjarstb : out std_logic;
--************************************************************************ --本段定義定義雙口RAM引腳
iol, iora, iorb : inout std_logic_vector(7 downto 0);
al, ara, arb : out std_logic_vector(13 downto 0);
cela, celb, cera, cerb : out std_logic;
oela, oelb, oera, oerb : out std_logic;
rwl, rwra, rwrb : out std_logic;
--************************************************************************ --本段定義ISA總線引腳
sd : inout std_logic_vector(7 downto 0);
sa : in std_logic_vector(19 downto 0);
ior, iow, aen, rstdrv : in std_logic);
end control;
architecture body_control of control is
signal base_address : std_logic_vector(4 downto 0); --基地址
signal cs_a, cs_b : std_logic; --A通道和B通道的片選信號
signal addressa,addressb : std_logic_vector(7 downto 0); --鎖存單片機地址總線低8位
signal top_a_up, top_b_up, top_a_down, top_b_down : std_logic_vector(12 downto 0); --堆棧區棧頂指針
signal top_a_up_step, top_b_up_step, top_a_down_step, top_b_down_step : std_logic_vector(12 downto 0); --棧頂當前操作位指針
signal buttom_a_up, buttom_b_up, buttom_a_down, buttom_b_down : std_logic_vector(12 downto 0); --堆棧區棧底指針
signal buttom_a_up_step, buttom_b_up_step,buttom_a_down_step,buttom_b_down_step : std_logic_vector(12 downto 0); --棧底當前操作位指針
signal commanda,commandaa, commandb, commandbb : std_logic_vector(3 downto 0); --命令字寄存器
signal stata,statb : std_logic_vector(2 downto 0); --狀態字寄存器
begin
--*************************************************************************
process(p2a)
begin
if alea'event and alea='0' then
addressa<=p0a;
end if;
oera<='0';
if p2a(7 downto 6)="01" then
cera<='0';
else
cera<='1';
end if;
if rda='0' then
rwra<='1';
else
rwra<=wra;
end if;
end process;
process(p2b)
begin
if aleb'event and aleb='0' then
addressb<=p0b;
end if;
oerb<='0';
if p2b(7 downto 6)="01" then
cerb<='0';
else
cerb<='1';
end if;
if rdb='0' then
rwrb<='1';
else
rwrb<=wrb;
end if;
end process;
ara<=p2a(5 downto 0)&addressa;
arb<=p2b(5 downto 0)&addressb;
process(wra)
variable data : std_logic_vector(7 downto 0);
begin
if p2a(7 downto 6)="01" and wra='0' then
data:=p0a;
else
data:=(others=>'Z');
end if;
iora<=data;
end process;
process(rda)
variable data : std_logic_vector(7 downto 0);
begin
if p2a(7 downto 6)="01" and rda='0' then
data:=iora;
else
data:=(others=>'Z');
end if;
p0a<=data;
end process;
process(wrb)
variable data : std_logic_vector(7 downto 0);
begin
if p2b(7 downto 6)="01" and wrb='0' then
data:=p0b;
else
data:=(others=>'Z');
end if;
iorb<=data;
end process;
process(rdb)
variable data : std_logic_vector(7 downto 0);
begin
if p2b(7 downto 6)="01" and rdb='0' then
data:=iorb;
else
data:=(others=>'Z');
end if;
p0b<=data;
end process;
--*******************************************************************
process(jp)
begin
case jp is
when "00000001" => base_address<="10000";
when "00000010" => base_address<="10001";
when "00000100" => base_address<="10010";
when "00001000" => base_address<="10011";
when "00010000" => base_address<="10100";
when "00100000" => base_address<="10101";
when "01000000" => base_address<="10110";
when "10000000" => base_address<="10111";
when others => null;
end case;
end process;
process(aen)
begin
cs_a<='1';
cs_b<='1';
if aen&sa(16 downto 0)="0000000"&base_address&"00001" then
cs_a<='0';
end if;
if aen&sa(16 downto 0)="0000000"&base_address&"00101" then
cs_b<='0';
end if;
oela<='0';
oelb<='0';
cela<=cs_a;
celb<=cs_b;
if ior='0' then
rwl<='1';
else
rwl<=iow;
end if;
end process;
process(ior)
variable data : std_logic_vector(7 downto 0);
begin
if cs_a='0' and ior='0' then
data:=iol;
else
data:=(others=>'Z');
end if;
sd<=data;
end process;
process(iow)
variable data : std_logic_vector(7 downto 0);
begin
if cs_a='0' and iow='0' then
data:=sd;
else
data:=(others=>'Z');
end if;
iol<=data;
end process;
process(ior)
variable data : std_logic_vector(3 downto 0);
begin
if aen&sa(16 downto 0)="0000000"&base_address&"00000" and ior='0' then
data:=commanda;
else
data:=(others=>'Z');
end if;
sd(3 downto 0)<=data;
end process;
process(iow)
variable data : std_logic_vector(3 downto 0);
begin
if aen&sa(16 downto 0)="0000000"&base_address&"00000" and iow='0' then
data:=sd(3 downto 0);
else
data:=(others=>'Z');
end if;
commandaa<=data;
end process;
process(commandaa)
variable data : std_logic_vector(3 downto 0);
begin
if commandaa(3)='1' then
data:="1000";
elsif commandaa(2)='1' then
data:="0100";
elsif commandaa(1)='1' then
data:="0010";
elsif commandaa(0)='1'then
data:="0001";
else
data:="0000";
end if;
commanda<=data;
end process;
process(ior)
variable data1 : std_logic_vector(3 downto 0);
begin
if aen&sa(16 downto 0)="00000001000000100" and ior='0' then
data1:=commandb;
else
data1:=(others=>'Z');
end if;
sd(3 downto 0)<=data1;
end process;
process(iow)
variable data2 : std_logic_vector(3 downto 0);
begin
if aen&sa(16 downto 0)="0000000"&base_address&"00100" and iow'event and iow='1' then
data2:=sd(3 downto 0);
else
data2:=(others=>'Z');
end if;
commandb<=data2;
end process;
process(ior)
variable data : std_logic_vector(2 downto 0);
begin
if aen&sa(16 downto 0)="0000000"&base_address&"00010" and ior='0' then
data:=stata;
else
data:=(others=>'Z');
end if;
sd(2 downto 0)<=data;
end process;
process(ior)
variable data : std_logic_vector(2 downto 0);
begin
if aen&sa(16 downto 0)="0000000"&base_address&"00110" and ior='0' then
data:=statb;
else
data:=(others=>'Z');
end if;
sd(2 downto 0)<=data;
end process;
end body_control;
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