{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 01 21:53:51 2007 " "Info: Processing started: Sat Dec 01 21:53:51 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off liushuideng -c liushuideng " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off liushuideng -c liushuideng" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "liushuideng.v(9) " "Warning (10268): Verilog HDL information at liushuideng.v(9): Always Construct contains both blocking and non-blocking assignments" {  } { { "liushuideng.v" "" { Text "E:/liushuideng/liushuideng.v" 9 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "liushuideng.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file liushuideng.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_led " "Info: Found entity 1: clk_led" {  } { { "liushuideng.v" "" { Text "E:/liushuideng/liushuideng.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Error" "ESGN_TOP_ENTITY_IS_MISSING" "liushuideng " "Error: Top-level design entity \"liushuideng\" is undefined" {  } {  } 0 0 "Top-level design entity \"%1!s!\" is undefined" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Sat Dec 01 21:53:51 2007 " "Error: Processing ended: Sat Dec 01 21:53:51 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/liushuideng/liushuideng.map.smsg " "Info: Generated suppressed messages file E:/liushuideng/liushuideng.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}