LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MOORE2 IS
  PORT(DATAIN:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
        CLK,RST:IN STD_LOGIC;
            Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END MOORE2;
ARCHITECTURE behav OF MOORE2 IS
   TYPE ST_TYPE IS(ST0,ST1,ST2,ST3,ST4);
     SIGNAL current_state,next_state:ST_TYPE;
      BEGIN
      REG:PROCESS(RST,CLK)
       BEGIN
       IF RST='1' THEN current_state<=ST0;
        ELSIF CLK'EVENT AND CLK='1' THEN
         current_state<=next_state;
       END IF;
      END PROCESS;
      COM:PROCESS(current_state,DATAIN)
	    BEGIN
		   CASE current_state IS
		    WHEN ST0=>IF DATAIN="10" THEN next_state<=ST1;
		      ELSE next_state<=ST0;END IF;
		      Q<="1001";
		    WHEN ST1=>IF DATAIN="11" THEN next_state<=ST2;
		      ELSE next_state<=ST1;END IF;
		      Q<="0101";
		    WHEN ST2=>IF DATAIN="01" THEN next_state<=ST3;
		      ELSE next_state<=ST0;END IF;
		      Q<="1100";
		    WHEN ST3=>IF DATAIN="00" THEN next_state<=ST4;
		      ELSE next_state<=ST2;END IF;
		      Q<="0010";
		    WHEN ST4=>IF DATAIN="11" THEN next_state<=ST4;
		      ELSE next_state<=ST3;END IF;
		      Q<="1001";
		    WHEN OTHERS=>next_state<=ST0;
		  END CASE;
	END PROCESS;
END behav;