?? part3.hier_info
字號:
|part3
SW[0] => SW[0]~13.IN2
SW[1] => SW[1]~12.IN2
SW[2] => SW[2]~11.IN2
SW[3] => SW[3]~10.IN2
SW[4] => SW[4]~9.IN2
SW[5] => SW[5]~8.IN2
SW[6] => SW[6]~7.IN2
SW[7] => SW[7]~6.IN2
SW[8] => ~NO_FANOUT~
SW[9] => ~NO_FANOUT~
SW[10] => ~NO_FANOUT~
SW[11] => SW[11]~5.IN2
SW[12] => SW[12]~4.IN2
SW[13] => SW[13]~3.IN2
SW[14] => SW[14]~2.IN2
SW[15] => SW[15]~1.IN2
SW[16] => ~NO_FANOUT~
SW[17] => SW[17]~0.IN1
KEY[0] => KEY[0]~0.IN1
KEY[1] => ~NO_FANOUT~
KEY[2] => ~NO_FANOUT~
KEY[3] => ~NO_FANOUT~
LEDG[0] <= SW[17]~0.DB_MAX_OUTPUT_PORT_TYPE
LEDG[1] <= <GND>
LEDG[2] <= <GND>
LEDG[3] <= <GND>
LEDG[4] <= <GND>
LEDG[5] <= <GND>
LEDG[6] <= <GND>
LEDG[7] <= <GND>
HEX0[0] <= SEG7_LUT:u6.oSEG
HEX0[1] <= SEG7_LUT:u6.oSEG
HEX0[2] <= SEG7_LUT:u6.oSEG
HEX0[3] <= SEG7_LUT:u6.oSEG
HEX0[4] <= SEG7_LUT:u6.oSEG
HEX0[5] <= SEG7_LUT:u6.oSEG
HEX0[6] <= SEG7_LUT:u6.oSEG
HEX1[0] <= SEG7_LUT:u5.oSEG
HEX1[1] <= SEG7_LUT:u5.oSEG
HEX1[2] <= SEG7_LUT:u5.oSEG
HEX1[3] <= SEG7_LUT:u5.oSEG
HEX1[4] <= SEG7_LUT:u5.oSEG
HEX1[5] <= SEG7_LUT:u5.oSEG
HEX1[6] <= SEG7_LUT:u5.oSEG
HEX2[0] <= <GND>
HEX2[1] <= <GND>
HEX2[2] <= <GND>
HEX2[3] <= <GND>
HEX2[4] <= <GND>
HEX2[5] <= <GND>
HEX2[6] <= <GND>
HEX3[0] <= <GND>
HEX3[1] <= <GND>
HEX3[2] <= <GND>
HEX3[3] <= <GND>
HEX3[4] <= <GND>
HEX3[5] <= <GND>
HEX3[6] <= <GND>
HEX4[0] <= SEG7_LUT:u4.oSEG
HEX4[1] <= SEG7_LUT:u4.oSEG
HEX4[2] <= SEG7_LUT:u4.oSEG
HEX4[3] <= SEG7_LUT:u4.oSEG
HEX4[4] <= SEG7_LUT:u4.oSEG
HEX4[5] <= SEG7_LUT:u4.oSEG
HEX4[6] <= SEG7_LUT:u4.oSEG
HEX5[0] <= SEG7_LUT:u3.oSEG
HEX5[1] <= SEG7_LUT:u3.oSEG
HEX5[2] <= SEG7_LUT:u3.oSEG
HEX5[3] <= SEG7_LUT:u3.oSEG
HEX5[4] <= SEG7_LUT:u3.oSEG
HEX5[5] <= SEG7_LUT:u3.oSEG
HEX5[6] <= SEG7_LUT:u3.oSEG
HEX6[0] <= SEG7_LUT:u1.oSEG
HEX6[1] <= SEG7_LUT:u1.oSEG
HEX6[2] <= SEG7_LUT:u1.oSEG
HEX6[3] <= SEG7_LUT:u1.oSEG
HEX6[4] <= SEG7_LUT:u1.oSEG
HEX6[5] <= SEG7_LUT:u1.oSEG
HEX6[6] <= SEG7_LUT:u1.oSEG
HEX7[0] <= SEG7_LUT:u2.oSEG
HEX7[1] <= SEG7_LUT:u2.oSEG
HEX7[2] <= SEG7_LUT:u2.oSEG
HEX7[3] <= SEG7_LUT:u2.oSEG
HEX7[4] <= SEG7_LUT:u2.oSEG
HEX7[5] <= SEG7_LUT:u2.oSEG
HEX7[6] <= SEG7_LUT:u2.oSEG
|part3|ram_single:u0
addr[0] => read_addr[0].DATAIN
addr[0] => mem_array.waddr[0].DATAIN
addr[0] => mem_array.WADDR
addr[0] => mem_array.RADDR
addr[1] => read_addr[1].DATAIN
addr[1] => mem_array.waddr[1].DATAIN
addr[1] => mem_array.WADDR1
addr[1] => mem_array.RADDR1
addr[2] => read_addr[2].DATAIN
addr[2] => mem_array.waddr[2].DATAIN
addr[2] => mem_array.WADDR2
addr[2] => mem_array.RADDR2
addr[3] => read_addr[3].DATAIN
addr[3] => mem_array.waddr[3].DATAIN
addr[3] => mem_array.WADDR3
addr[3] => mem_array.RADDR3
addr[4] => read_addr[4].DATAIN
addr[4] => mem_array.waddr[4].DATAIN
addr[4] => mem_array.WADDR4
addr[4] => mem_array.RADDR4
data[0] => mem_array.datain[0].DATAIN
data[0] => mem_array.DATAIN
data[1] => mem_array.datain[1].DATAIN
data[1] => mem_array.DATAIN1
data[2] => mem_array.datain[2].DATAIN
data[2] => mem_array.DATAIN2
data[3] => mem_array.datain[3].DATAIN
data[3] => mem_array.DATAIN3
data[4] => mem_array.datain[4].DATAIN
data[4] => mem_array.DATAIN4
data[5] => mem_array.datain[5].DATAIN
data[5] => mem_array.DATAIN5
data[6] => mem_array.datain[6].DATAIN
data[6] => mem_array.DATAIN6
data[7] => mem_array.datain[7].DATAIN
data[7] => mem_array.DATAIN7
we => always0~0.DATAIN
we => mem_array.WE
clock => mem_array.datain[6].CLK
clock => mem_array.datain[5].CLK
clock => mem_array.datain[4].CLK
clock => mem_array.datain[3].CLK
clock => mem_array.datain[2].CLK
clock => mem_array.datain[1].CLK
clock => mem_array.datain[0].CLK
clock => mem_array.waddr[4].CLK
clock => mem_array.waddr[3].CLK
clock => mem_array.waddr[2].CLK
clock => mem_array.waddr[1].CLK
clock => mem_array.waddr[0].CLK
clock => always0~0.CLK
clock => read_addr[4].CLK
clock => read_addr[3].CLK
clock => read_addr[2].CLK
clock => read_addr[1].CLK
clock => read_addr[0].CLK
clock => mem_array.datain[7].CLK
clock => mem_array.CLK0
clock => mem_array.CLK1
q[0] <= mem_array.DATAOUT
q[1] <= mem_array.DATAOUT1
q[2] <= mem_array.DATAOUT2
q[3] <= mem_array.DATAOUT3
q[4] <= mem_array.DATAOUT4
q[5] <= mem_array.DATAOUT5
q[6] <= mem_array.DATAOUT6
q[7] <= mem_array.DATAOUT7
|part3|SEG7_LUT:u1
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0
|part3|SEG7_LUT:u2
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0
|part3|SEG7_LUT:u3
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0
|part3|SEG7_LUT:u4
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0
|part3|SEG7_LUT:u5
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0
|part3|SEG7_LUT:u6
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0
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