Classic Timing Analyzer report for Uart
Thu Feb 28 16:00:08 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. tsu
  7. tco
  8. th
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                            ;
+------------------------------+-------+---------------+----------------------------------+------------------------+--------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From                   ; To                       ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+------------------------+--------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 1.829 ns                         ; txdbuf_in[0]           ; transfer:inst2|txds      ; --         ; clk      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 11.935 ns                        ; reciever:inst1|rbuf[0] ; rec_buf[0]               ; clk        ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; 3.039 ns                         ; reset                  ; transfer:inst2|xcnt16[0] ; --         ; clk      ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; 203.42 MHz ( period = 4.916 ns ) ; baud:inst|cnt[0]       ; baud:inst|cnt[30]        ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                        ;                          ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+------------------------+--------------------------+------------+----------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;