?? compare_8_bits.tan.rpt
字號:
Timing Analyzer report for Compare_8_bits
Tue Aug 08 13:27:34 2006
Version 4.2 Build 157 12/07/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 13.300 ns ; B[0] ; LT ; ; ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM7032SLC44-5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minumum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Clock Analysis Only ; Off ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off clear and preset signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Do Min/Max analysis using Rise/Fall delays ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Use Clock Latency for PLL offset ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+---------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A ; None ; 13.300 ns ; A[0] ; LT ;
; N/A ; None ; 13.300 ns ; B[0] ; LT ;
; N/A ; None ; 12.800 ns ; A[5] ; LT ;
; N/A ; None ; 12.800 ns ; B[5] ; LT ;
; N/A ; None ; 12.800 ns ; A[3] ; LT ;
; N/A ; None ; 12.800 ns ; B[3] ; LT ;
; N/A ; None ; 12.800 ns ; A[4] ; LT ;
; N/A ; None ; 12.800 ns ; B[4] ; LT ;
; N/A ; None ; 12.800 ns ; A[2] ; LT ;
; N/A ; None ; 12.800 ns ; B[2] ; LT ;
; N/A ; None ; 12.800 ns ; A[1] ; LT ;
; N/A ; None ; 12.800 ns ; B[1] ; LT ;
; N/A ; None ; 12.800 ns ; A[5] ; GT ;
; N/A ; None ; 12.800 ns ; B[5] ; GT ;
; N/A ; None ; 12.800 ns ; A[3] ; GT ;
; N/A ; None ; 12.800 ns ; B[3] ; GT ;
; N/A ; None ; 12.800 ns ; A[4] ; GT ;
; N/A ; None ; 12.800 ns ; B[4] ; GT ;
; N/A ; None ; 12.800 ns ; A[2] ; GT ;
; N/A ; None ; 12.800 ns ; B[2] ; GT ;
; N/A ; None ; 12.800 ns ; A[1] ; GT ;
; N/A ; None ; 12.800 ns ; B[1] ; GT ;
; N/A ; None ; 12.400 ns ; A[0] ; GT ;
; N/A ; None ; 12.400 ns ; B[0] ; GT ;
; N/A ; None ; 10.600 ns ; A[7] ; LT ;
; N/A ; None ; 10.600 ns ; B[7] ; LT ;
; N/A ; None ; 10.600 ns ; A[6] ; LT ;
; N/A ; None ; 10.600 ns ; B[6] ; LT ;
; N/A ; None ; 9.700 ns ; A[7] ; GT ;
; N/A ; None ; 9.700 ns ; B[7] ; GT ;
; N/A ; None ; 9.700 ns ; A[6] ; GT ;
; N/A ; None ; 9.700 ns ; B[6] ; GT ;
; N/A ; None ; 7.800 ns ; A[0] ; EQ ;
; N/A ; None ; 7.800 ns ; B[0] ; EQ ;
; N/A ; None ; 6.900 ns ; A[2] ; EQ ;
; N/A ; None ; 6.900 ns ; B[2] ; EQ ;
; N/A ; None ; 6.900 ns ; A[1] ; EQ ;
; N/A ; None ; 6.900 ns ; B[1] ; EQ ;
; N/A ; None ; 6.000 ns ; A[5] ; EQ ;
; N/A ; None ; 6.000 ns ; B[5] ; EQ ;
; N/A ; None ; 6.000 ns ; A[3] ; EQ ;
; N/A ; None ; 6.000 ns ; B[3] ; EQ ;
; N/A ; None ; 6.000 ns ; A[4] ; EQ ;
; N/A ; None ; 6.000 ns ; B[4] ; EQ ;
; N/A ; None ; 5.100 ns ; A[7] ; EQ ;
; N/A ; None ; 5.100 ns ; B[7] ; EQ ;
; N/A ; None ; 5.100 ns ; A[6] ; EQ ;
; N/A ; None ; 5.100 ns ; B[6] ; EQ ;
+-------+-------------------+-----------------+------+----+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
Info: Processing started: Tue Aug 08 13:27:34 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off Compare_8_bits -c Compare_8_bits
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Longest tpd from source pin "A[0]" to destination pin "LT" is 13.300 ns
Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 6; PIN Node = 'A[0]'
Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.900 ns; Loc. = LC3; Fanout = 1; COMB Node = 'reduce_nor~47'
Info: 3: + IC(0.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC4; Fanout = 1; COMB Node = 'reduce_nor~49'
Info: 4: + IC(0.000 ns) + CELL(0.900 ns) = 5.700 ns; Loc. = LC5; Fanout = 1; COMB Node = 'reduce_nor~55'
Info: 5: + IC(0.000 ns) + CELL(1.900 ns) = 7.600 ns; Loc. = LC6; Fanout = 9; COMB Node = 'reduce_nor~32'
Info: 6: + IC(1.000 ns) + CELL(2.600 ns) = 11.200 ns; Loc. = LC9; Fanout = 1; COMB Node = 'LT~17'
Info: 7: + IC(0.000 ns) + CELL(1.900 ns) = 13.100 ns; Loc. = LC10; Fanout = 1; COMB Node = 'LT~16'
Info: 8: + IC(0.000 ns) + CELL(0.200 ns) = 13.300 ns; Loc. = PIN_14; Fanout = 0; PIN Node = 'LT'
Info: Total cell delay = 11.200 ns ( 84.21 % )
Info: Total interconnect delay = 2.100 ns ( 15.79 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Tue Aug 08 13:27:34 2006
Info: Elapsed time: 00:00:01
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -