---------------------------------------------------------------------------------- Purpose : synthesizable CRC function--   * polynomial: (0 4 5 8)--   * data width: 1-- convention: the first serial bit is D[0]--------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;package PCK_CRC8_D1 is  function nextCRC8_D1    (Data: std_logic;--當前位     crc:  std_logic_vector(7 downto 0))--校驗完前一位所得的CRC校驗碼（若當期位為第一位，則CRC為0）    return std_logic_vector;end PCK_CRC8_D1;--------------------------------------------------------------------------------package body PCK_CRC8_D1 is  function nextCRC8_D1    (Data: std_logic;     crc:  std_logic_vector(7 downto 0))    return std_logic_vector is    variable d:      std_logic_vector(0 downto 0);    variable c:      std_logic_vector(7 downto 0);    variable newcrc: std_logic_vector(7 downto 0);--------------------------------------------------------------------------------  begin    d(0) := Data;    c := crc;    newcrc(0) := d(0) xor c(7);    newcrc(1) := c(0);    newcrc(2) := c(1);    newcrc(3) := c(2);    newcrc(4) := d(0) xor c(3) xor c(7);    newcrc(5) := d(0) xor c(4) xor c(7);    newcrc(6) := c(5);    newcrc(7) := c(6);    return newcrc;  end nextCRC8_D1;end PCK_CRC8_D1;