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-- Company: 
-- Engineer: Michael Ye
-- 
-- Create Date:    14:54:20 06/20/2007 
-- Design Name: 
-- Module Name:    disp - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration IF instantiating
---- any Xilinx primitives IN this code

ENTITY disp IS
	Port (
		reset		:	IN	STD_LOGIC;
		clk		:	IN STD_LOGIC;
		data_in 	:	IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		addr_out :	OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
		red 		:	OUT STD_LOGIC;
		green 	:	OUT STD_LOGIC;
		blue 		:	OUT STD_LOGIC;
		Hsync 	:	OUT STD_LOGIC;
		Vsync 	:	OUT STD_LOGIC
		);
END disp;

ARCHITECTURE Behavioral OF disp IS

	SIGNAL counter_h : STD_LOGIC_VECTOR (10 DOWNTO 0);	SIGNAL counter_v : STD_LOGIC_VECTOR (10 DOWNTO 0);
	SIGNAL address	  : STD_LOGIC_VECTOR (14 DOWNTO 0);
	SIGNAL data_temp : STD_LOGIC_VECTOR (3 DOWNTO 0);
	SIGNAL data		  : STD_LOGIC_VECTOR (7 DOWNTO 0);

BEGIN

	PROCESS(clk,reset)BEGIN
			IF(clk'event AND clk='1')THEN
				data<=data_in;
			END IF;
	END PROCESS;

	PROCESS(clk,reset)BEGIN
		IF(clk'event AND clk='1')THEN
			IF(reset='1')THEN
				counter_h<="00000000000";
				counter_v<="00000000000";
			ELSE
				IF(counter_h<800)THEN
					counter_h<=counter_h+1;
				ELSE
					counter_h<="00000000000";
					IF(counter_v<521)THEN
						counter_v<=counter_v+'1';
					ELSE
						counter_v<="00000000000";
					END IF;
				END IF;
			END IF;
		END IF;
	END PROCESS;

	PROCESS(clk,reset)BEGIN
		IF(clk'event AND clk='1')THEN
			IF(counter_h<96)THEN
				Hsync<='0';
			ELSE
				Hsync<='1';
			END IF;
		END IF;
	END PROCESS;
	PROCESS(clk,reset)BEGIN
		IF(clk'event AND clk='1')THEN
			IF(counter_v>1)THEN
				Vsync<='1';
			ELSE
				Vsync<='0';
			END IF;
		END IF;
	END PROCESS;

	PROCESS(clk,reset)BEGIN
		IF(clk'event AND clk='1')THEN
			IF(reset='1' OR counter_v<11)THEN
				address<="000000000000000";
			ELSE
				IF(counter_v>30 AND counter_v<431 AND counter_h>143 AND counter_h<783 AND counter_h(1 DOWNTO 0)="00")THEN					IF(address<32000)THEN
						IF(counter_h=780 AND counter_v(0)='1')THEN
							address<=address-159;
						ELSE
							address<=address+'1';
						END IF;
					ELSE
						address<="000000000000000";
					END IF;
				END IF;
			END IF;
		END IF;
	END PROCESS;

	PROCESS(clk)BEGIN--divide high bits AND low bits
		IF(clk'event AND clk='1')THEN
			IF(counter_v>30 AND counter_v<431)THEN
				IF(counter_h(1 DOWNTO 0)="01" OR counter_h(1 DOWNTO 0)="10")THEN
					data_temp<=data(3 DOWNTO 0);
				ELSE
					data_temp<=data(7 DOWNTO 4);
				END IF;
			ELSE
				IF(counter_v<11)THEN
					data_temp<="0000";
				ELSE
					data_temp<="0000";
				END IF;
			END IF;
		END IF;
	END PROCESS;

	PROCESS(clk)BEGIN
		IF(clk'event AND clk='1')THEN
			IF(counter_h>143 AND counter_h<784)THEN
				blue<=data_temp(0);
				green<=data_temp(1);
				red<=data_temp(2);
			ELSE
				blue<='0';
				green<='0';
				red<='0';
			END IF;
		END IF;
	END PROCESS;

addr_out<=address;	

END Behavioral;