--G1_q[7] is lpm_counter:pc_rtl_0|alt_synch_counter:wysi_counter|q[7]
--operation mode is normal

G1_q[7]_lut_out = G1_q[7] $ G1L51;
G1_q[7]_sload_eqn = (A1L781 & reg_C[7]) # (!A1L781 & G1_q[7]_lut_out);
G1_q[7] = DFFE(G1_q[7]_sload_eqn, clock, reset, , state);


--G1_q[6] is lpm_counter:pc_rtl_0|alt_synch_counter:wysi_counter|q[6]
--operation mode is counter

G1_q[6]_lut_out = G1_q[6] $ !G1L31;
G1_q[6]_sload_eqn = (A1L781 & reg_C[6]) # (!A1L781 & G1_q[6]_lut_out);
G1_q[6] = DFFE(G1_q[6]_sload_eqn, clock, reset, , state);

--G1L51 is lpm_counter:pc_rtl_0|alt_synch_counter:wysi_counter|counter_cell[6]~COUT
--operation mode is counter

G1L51 = CARRY(G1_q[6] & !G1L31);


--G1_q[5] is lpm_counter:pc_rtl_0|alt_synch_counter:wysi_counter|q[5]
--operation mode is counter

G1_q[5]_lut_out = G1_q[5] $ G1L11;
G1_q[5]_sload_eqn = (A1L781 & reg_C[5]) # (!A1L781 & G1_q[5]_lut_out);
G1_q[5] = DFFE(G1_q[5]_sload_eqn, clock, reset, , state);

--G1L31 is lpm_counter:pc_rtl_0|alt_synch_counter:wysi_counter|counter_cell[5]~COUT
--operation mode is counter

G1L31 = CARRY(!G1L11 # !G1_q[5]);


--G1_q[4] is lpm_counter:pc_rtl_0|alt_synch_counter:wysi_counter|q[4]
--operation mode is counter

G1_q[4]_lut_out = G1_q[4] $ !G1L9;
G1_q[4]_sload_eqn = (A1L781 & reg_C[4]) # (!A1L781 & G1_q[4]_lut_out);
G1_q[4] = DFFE(G1_q[4]_sload_eqn, clock, reset, , state);

--G1L11 is lpm_counter:pc_rtl_0|alt_synch_counter:wysi_counter|counter_cell[4]~COUT
--operation mode is counter

G1L11 = CARRY(G1_q[4] & !G1L9);


--G1_q[3] is lpm_counter:pc_rtl_0|alt_synch_counter:wysi_counter|q[3]
--operation mode is counter

G1_q[3]_lut_out = G1_q[3] $ G1L7;
G1_q[3]_sload_eqn = (A1L781 & reg_C[3]) # (!A1L781 & G1_q[3]_lut_out);
G1_q[3] = DFFE(G1_q[3]_sload_eqn, clock, reset, , state);

--G1L9 is lpm_counter:pc_rtl_0|alt_synch_counter:wysi_counter|counter_cell[3]~COUT
--operation mode is counter

G1L9 = CARRY(!G1L7 # !G1_q[3]);


--G1_q[2] is lpm_counter:pc_rtl_0|alt_synch_counter:wysi_counter|q[2]
--operation mode is counter

G1_q[2]_lut_out = G1_q[2] $ !G1L5;
G1_q[2]_sload_eqn = (A1L781 & reg_C[2]) # (!A1L781 & G1_q[2]_lut_out);
G1_q[2] = DFFE(G1_q[2]_sload_eqn, clock, reset, , state);

--G1L7 is lpm_counter:pc_rtl_0|alt_synch_counter:wysi_counter|counter_cell[2]~COUT
--operation mode is counter

G1L7 = CARRY(G1_q[2] & !G1L5);


--G1_q[1] is lpm_counter:pc_rtl_0|alt_synch_counter:wysi_counter|q[1]
--operation mode is counter

G1_q[1]_lut_out = G1_q[1] $ G1L3;
G1_q[1]_sload_eqn = (A1L781 & reg_C[1]) # (!A1L781 & G1_q[1]_lut_out);
G1_q[1] = DFFE(G1_q[1]_sload_eqn, clock, reset, , state);

--G1L5 is lpm_counter:pc_rtl_0|alt_synch_counter:wysi_counter|counter_cell[1]~COUT
--operation mode is counter

G1L5 = CARRY(!G1L3 # !G1_q[1]);


--G1_q[0] is lpm_counter:pc_rtl_0|alt_synch_counter:wysi_counter|q[0]
--operation mode is qfbk_counter

G1_q[0]_lut_out = !G1_q[0];
G1_q[0]_sload_eqn = (A1L781 & reg_C[0]) # (!A1L781 & G1_q[0]_lut_out);
G1_q[0] = DFFE(G1_q[0]_sload_eqn, clock, reset, , state);

--G1L3 is lpm_counter:pc_rtl_0|alt_synch_counter:wysi_counter|counter_cell[0]~COUT
--operation mode is qfbk_counter

G1L3 = CARRY(G1_q[0]);


--reg_C[7] is reg_C[7]
--operation mode is normal

reg_C[7]_lut_out = F3_cs_buffer[7];
reg_C[7] = DFFE(reg_C[7]_lut_out, clock, reset, , state);


--reg_C[6] is reg_C[6]
--operation mode is normal

reg_C[6]_lut_out = F3_cs_buffer[6];
reg_C[6] = DFFE(reg_C[6]_lut_out, clock, reset, , state);


--reg_C[5] is reg_C[5]
--operation mode is normal

reg_C[5]_lut_out = F3_cs_buffer[5];
reg_C[5] = DFFE(reg_C[5]_lut_out, clock, reset, , state);


--reg_C[4] is reg_C[4]
--operation mode is normal

reg_C[4]_lut_out = F3_cs_buffer[4];
reg_C[4] = DFFE(reg_C[4]_lut_out, clock, reset, , state);


--reg_C[3] is reg_C[3]
--operation mode is normal

reg_C[3]_lut_out = F3_cs_buffer[3];
reg_C[3] = DFFE(reg_C[3]_lut_out, clock, reset, , state);


--reg_C[2] is reg_C[2]
--operation mode is normal

reg_C[2]_lut_out = F3_cs_buffer[2];
reg_C[2] = DFFE(reg_C[2]_lut_out, clock, reset, , state);


--reg_C[1] is reg_C[1]
--operation mode is normal

reg_C[1]_lut_out = F3_cs_buffer[1];
reg_C[1] = DFFE(reg_C[1]_lut_out, clock, reset, , state);


--reg_C[0] is reg_C[0]
--operation mode is normal

reg_C[0]_lut_out = F3_cs_buffer[0];
reg_C[0] = DFFE(reg_C[0]_lut_out, clock, reset, , state);


--smdr1[15] is smdr1[15]
--operation mode is normal

smdr1[15]_lut_out = smdr[15];
smdr1[15] = DFFE(smdr1[15]_lut_out, clock, reset, , A1L627);


--smdr1[14] is smdr1[14]
--operation mode is normal

smdr1[14]_lut_out = smdr[14];
smdr1[14] = DFFE(smdr1[14]_lut_out, clock, reset, , A1L627);


--smdr1[13] is smdr1[13]
--operation mode is normal

smdr1[13]_lut_out = smdr[13];
smdr1[13] = DFFE(smdr1[13]_lut_out, clock, reset, , A1L627);


--smdr1[12] is smdr1[12]
--operation mode is normal

smdr1[12]_lut_out = smdr[12];
smdr1[12] = DFFE(smdr1[12]_lut_out, clock, reset, , A1L627);


--smdr1[11] is smdr1[11]
--operation mode is normal

smdr1[11]_lut_out = smdr[11];
smdr1[11] = DFFE(smdr1[11]_lut_out, clock, reset, , A1L627);


--smdr1[10] is smdr1[10]
--operation mode is normal

smdr1[10]_lut_out = smdr[10];
smdr1[10] = DFFE(smdr1[10]_lut_out, clock, reset, , A1L627);


--smdr1[9] is smdr1[9]
--operation mode is normal

smdr1[9]_lut_out = smdr[9];
smdr1[9] = DFFE(smdr1[9]_lut_out, clock, reset, , A1L627);


--smdr1[8] is smdr1[8]
--operation mode is normal

smdr1[8]_lut_out = smdr[8];
smdr1[8] = DFFE(smdr1[8]_lut_out, clock, reset, , A1L627);


--smdr1[7] is smdr1[7]
--operation mode is normal

smdr1[7]_lut_out = smdr[7];
smdr1[7] = DFFE(smdr1[7]_lut_out, clock, reset, , A1L627);


--smdr1[6] is smdr1[6]
--operation mode is normal

smdr1[6]_lut_out = smdr[6];
smdr1[6] = DFFE(smdr1[6]_lut_out, clock, reset, , A1L627);


--smdr1[5] is smdr1[5]
--operation mode is normal

smdr1[5]_lut_out = smdr[5];
smdr1[5] = DFFE(smdr1[5]_lut_out, clock, reset, , A1L627);


--smdr1[4] is smdr1[4]
--operation mode is normal

smdr1[4]_lut_out = smdr[4];
smdr1[4] = DFFE(smdr1[4]_lut_out, clock, reset, , A1L627);


--smdr1[3] is smdr1[3]
--operation mode is normal

smdr1[3]_lut_out = smdr[3];
smdr1[3] = DFFE(smdr1[3]_lut_out, clock, reset, , A1L627);


--smdr1[2] is smdr1[2]
--operation mode is normal

smdr1[2]_lut_out = smdr[2];
smdr1[2] = DFFE(smdr1[2]_lut_out, clock, reset, , A1L627);


--smdr1[1] is smdr1[1]
--operation mode is normal

smdr1[1]_lut_out = smdr[1];
smdr1[1] = DFFE(smdr1[1]_lut_out, clock, reset, , A1L627);


--smdr1[0] is smdr1[0]
--operation mode is normal

smdr1[0]_lut_out = smdr[0];
smdr1[0] = DFFE(smdr1[0]_lut_out, clock, reset, , A1L627);


--dw is dw
--operation mode is normal

dw_lut_out = !A1L585 & ex_ir[11];
dw = DFFE(dw_lut_out, clock, reset, , state);


--reg_C[15] is reg_C[15]
--operation mode is normal

reg_C[15]_lut_out = D1_unreg_res_node[15];
reg_C[15] = DFFE(reg_C[15]_lut_out, clock, reset, , state);


--reg_B[15] is reg_B[15]
--operation mode is normal

reg_B[15]_lut_out = A1L384 & (A1L652 # A1L552 & A1L982) # !A1L384 & A1L552 & A1L982;
reg_B[15] = DFFE(reg_B[15]_lut_out, clock, reset, , state);


--reg_A[15] is reg_A[15]
--operation mode is normal

reg_A[15]_lut_out = !A1L391;
reg_A[15] = DFFE(reg_A[15]_lut_out, clock, reset, , state);


--A1L445 is i~5942
--operation mode is normal

A1L445 = reg_B[15] & (reg_A[15] # select_y[0]) # !reg_B[15] & reg_A[15] & !select_y[0];


--A1L545 is i~5943
--operation mode is normal

A1L545 = select_y[1] & reg_C[15] & select_y[0] # !select_y[1] & A1L445;


--gr[6][15] is gr[6][15]
--operation mode is normal

gr[6][15]_lut_out = reg_C1[15];
gr[6][15] = DFFE(gr[6][15]_lut_out, clock, reset, , A1L461);


--gr[5][15] is gr[5][15]
--operation mode is normal

gr[5][15]_lut_out = reg_C1[15];
gr[5][15] = DFFE(gr[5][15]_lut_out, clock, reset, , A1L641);


--gr[4][15] is gr[4][15]
--operation mode is normal

gr[4][15]_lut_out = reg_C1[15];
gr[4][15] = DFFE(gr[4][15]_lut_out, clock, reset, , A1L821);


--A1L243 is i~465
--operation mode is normal

A1L243 = select_y[0] & (select_y[1] # gr[5][15]) # !select_y[0] & !select_y[1] & gr[4][15];


--gr[7][15] is gr[7][15]
--operation mode is normal

gr[7][15]_lut_out = reg_C1[15];
gr[7][15] = DFFE(gr[7][15]_lut_out, clock, reset, , A1L281);


--A1L343 is i~466
--operation mode is normal

A1L343 = A1L243 & (gr[7][15] # !select_y[1]) # !A1L243 & gr[6][15] & select_y[1];


--gr[3][15] is gr[3][15]
--operation mode is normal

gr[3][15]_lut_out = reg_C1[15];
gr[3][15] = DFFE(gr[3][15]_lut_out, clock, reset, , A1L011);


--gr[1][15] is gr[1][15]
--operation mode is normal

gr[1][15]_lut_out = reg_C1[15];
gr[1][15] = DFFE(gr[1][15]_lut_out, clock, reset, , A1L47);


--A1L645 is i~5944
--operation mode is normal

A1L645 = gr[3][15] & (gr[1][15] # select_y[1]) # !gr[3][15] & gr[1][15] & !select_y[1];


--gr[2][15] is gr[2][15]
--operation mode is normal

gr[2][15]_lut_out = reg_C1[15];
gr[2][15] = DFFE(gr[2][15]_lut_out, clock, reset, , A1L29);


--A1L745 is i~5945
--operation mode is normal

A1L745 = select_y[0] & A1L645 # !select_y[0] & gr[2][15] & select_y[1];


--A1L043 is i~463
--operation mode is normal

A1L043 = select_y[2] & (select_y[3] # A1L343) # !select_y[2] & !select_y[3] & A1L745;


--id_ir[15] is id_ir[15]
--operation mode is normal

id_ir[15]_lut_out = i_datain[15];
id_ir[15] = DFFE(id_ir[15]_lut_out, clock, reset, , state);


--reg_C1[15] is reg_C1[15]
--operation mode is normal

reg_C1[15]_lut_out = mem_ir[11] & reg_C[15] # !mem_ir[11] & (A1L785 & reg_C[15] # !A1L785 & d_datain[15]);
reg_C1[15] = DFFE(reg_C1[15]_lut_out, clock, reset, , state);


--A1L845 is i~5946
--operation mode is normal

A1L845 = id_ir[15] & (reg_C1[15] # select_y[1]) # !id_ir[15] & reg_C1[15] & !select_y[1];


--smdr[15] is smdr[15]
--operation mode is normal

smdr[15]_lut_out = A1L944 & (A1L985 # id_ir[10]) # !A1L944 & A1L985 & !id_ir[10];
smdr[15] = DFFE(smdr[15]_lut_out, clock, reset, , A1L347);


--A1L945 is i~5947
--operation mode is normal

A1L945 = select_y[0] & smdr[15] & !select_y[1] # !select_y[0] & A1L845;


--A1L143 is i~464
--operation mode is normal

A1L143 = A1L043 & (A1L945 # !select_y[3]) # !A1L043 & A1L545 & select_y[3];


--reg_C[14] is reg_C[14]
--operation mode is normal

reg_C[14]_lut_out = F3_cs_buffer[14];
reg_C[14] = DFFE(reg_C[14]_lut_out, clock, reset, , state);


--reg_B[14] is reg_B[14]
--operation mode is normal

reg_B[14]_lut_out = A1L652 & (A1L784 # A1L982 & A1L952) # !A1L652 & A1L982 & A1L952;
reg_B[14] = DFFE(reg_B[14]_lut_out, clock, reset, , state);


--reg_A[14] is reg_A[14]
--operation mode is normal

reg_A[14]_lut_out = !A1L791;
reg_A[14] = DFFE(reg_A[14]_lut_out, clock, reset, , state);


--A1L055 is i~5948
--operation mode is normal

A1L055 = reg_B[14] & (reg_A[14] # select_y[0]) # !reg_B[14] & reg_A[14] & !select_y[0];


--A1L155 is i~5949
--operation mode is normal

A1L155 = select_y[1] & select_y[0] & reg_C[14] # !select_y[1] & A1L055;


--gr[6][14] is gr[6][14]
--operation mode is normal

gr[6][14]_lut_out = reg_C1[14];
gr[6][14] = DFFE(gr[6][14]_lut_out, clock, reset, , A1L461);


--gr[5][14] is gr[5][14]
--operation mode is normal

gr[5][14]_lut_out = reg_C1[14];
gr[5][14] = DFFE(gr[5][14]_lut_out, clock, reset, , A1L641);


--gr[4][14] is gr[4][14]
--operation mode is normal

gr[4][14]_lut_out = reg_C1[14];
gr[4][14] = DFFE(gr[4][14]_lut_out, clock, reset, , A1L821);


--A1L643 is i~469
--operation mode is normal

A1L643 = select_y[0] & (select_y[1] # gr[5][14]) # !select_y[0] & !select_y[1] & gr[4][14];


--gr[7][14] is gr[7][14]
--operation mode is normal

gr[7][14]_lut_out = reg_C1[14];
gr[7][14] = DFFE(gr[7][14]_lut_out, clock, reset, , A1L281);


--A1L743 is i~470
--operation mode is normal

A1L743 = A1L643 & (gr[7][14] # !select_y[1]) # !A1L643 & gr[6][14] & select_y[1];


--gr[3][14] is gr[3][14]
--operation mode is normal

gr[3][14]_lut_out = reg_C1[14];
gr[3][14] = DFFE(gr[3][14]_lut_out, clock, reset, , A1L011);


--gr[1][14] is gr[1][14]
--operation mode is normal

gr[1][14]_lut_out = reg_C1[14];
gr[1][14] = DFFE(gr[1][14]_lut_out, clock, reset, , A1L47);


--A1L255 is i~5950
--operation mode is normal

A1L255 = gr[3][14] & (gr[1][14] # select_y[1]) # !gr[3][14] & gr[1][14] & !select_y[1];


--gr[2][14] is gr[2][14]
--operation mode is normal

gr[2][14]_lut_out = reg_C1[14];
gr[2][14] = DFFE(gr[2][14]_lut_out, clock, reset, , A1L29);


--A1L355 is i~5951
--operation mode is normal

A1L355 = select_y[0] & A1L255 # !select_y[0] & select_y[1] & gr[2][14];


--A1L443 is i~467
--operation mode is normal

A1L443 = select_y[2] & (select_y[3] # A1L743) # !select_y[2] & !select_y[3] & A1L355;


--id_ir[14] is id_ir[14]
--operation mode is normal

id_ir[14]_lut_out = i_datain[14];
id_ir[14] = DFFE(id_ir[14]_lut_out, clock, reset, , state);


--reg_C1[14] is reg_C1[14]
--operation mode is normal

reg_C1[14]_lut_out = mem_ir[11] & reg_C[14] # !mem_ir[11] & (A1L785 & reg_C[14] # !A1L785 & d_datain[14]);
reg_C1[14] = DFFE(reg_C1[14]_lut_out, clock, reset, , state);