gr[3][10]_lut_out = reg_C1[10];
gr[3][10] = DFFE(gr[3][10]_lut_out, clock, reset, , A1L011);


--gr[1][10] is gr[1][10]
--operation mode is normal

gr[1][10]_lut_out = reg_C1[10];
gr[1][10] = DFFE(gr[1][10]_lut_out, clock, reset, , A1L47);


--A1L175 is i~5969
--operation mode is normal

A1L175 = gr[3][10] & (gr[1][10] # select_y[1]) # !gr[3][10] & gr[1][10] & !select_y[1];


--gr[2][10] is gr[2][10]
--operation mode is normal

gr[2][10]_lut_out = reg_C1[10];
gr[2][10] = DFFE(gr[2][10]_lut_out, clock, reset, , A1L29);


--A1L275 is i~5970
--operation mode is normal

A1L275 = select_y[0] & A1L175 # !select_y[0] & select_y[1] & gr[2][10];


--A1L463 is i~487
--operation mode is normal

A1L463 = select_y[2] & (select_y[3] # A1L763) # !select_y[2] & !select_y[3] & A1L275;


--id_ir[10] is id_ir[10]
--operation mode is normal

id_ir[10]_lut_out = i_datain[10];
id_ir[10] = DFFE(id_ir[10]_lut_out, clock, reset, , state);


--reg_C1[10] is reg_C1[10]
--operation mode is normal

reg_C1[10]_lut_out = mem_ir[11] & reg_C[10] # !mem_ir[11] & (A1L785 & reg_C[10] # !A1L785 & d_datain[10]);
reg_C1[10] = DFFE(reg_C1[10]_lut_out, clock, reset, , state);


--A1L375 is i~5971
--operation mode is normal

A1L375 = id_ir[10] & (reg_C1[10] # select_y[1]) # !id_ir[10] & reg_C1[10] & !select_y[1];


--smdr[10] is smdr[10]
--operation mode is normal

smdr[10]_lut_out = A1L954 & (A1L995 # id_ir[10]) # !A1L954 & A1L995 & !id_ir[10];
smdr[10] = DFFE(smdr[10]_lut_out, clock, reset, , A1L347);


--A1L475 is i~5972
--operation mode is normal

A1L475 = select_y[0] & smdr[10] & !select_y[1] # !select_y[0] & A1L375;


--A1L563 is i~488
--operation mode is normal

A1L563 = A1L463 & (A1L475 # !select_y[3]) # !A1L463 & A1L075 & select_y[3];


--reg_B[9] is reg_B[9]
--operation mode is normal

reg_B[9]_lut_out = A1L652 & (A1L705 # A1L982 & A1L962) # !A1L652 & A1L982 & A1L962;
reg_B[9] = DFFE(reg_B[9]_lut_out, clock, reset, , state);


--reg_C1[9] is reg_C1[9]
--operation mode is normal

reg_C1[9]_lut_out = mem_ir[11] & reg_C[9] # !mem_ir[11] & (A1L785 & reg_C[9] # !A1L785 & d_datain[9]);
reg_C1[9] = DFFE(reg_C1[9]_lut_out, clock, reset, , state);


--reg_A[9] is reg_A[9]
--operation mode is normal

reg_A[9]_lut_out = !A1L712;
reg_A[9] = DFFE(reg_A[9]_lut_out, clock, reset, , state);


--A1L473 is i~497
--operation mode is normal

A1L473 = select_y[2] & (select_y[0] # reg_C1[9]) # !select_y[2] & !select_y[0] & reg_A[9];


--smdr[9] is smdr[9]
--operation mode is normal

smdr[9]_lut_out = A1L164 & (A1L106 # id_ir[10]) # !A1L164 & A1L106 & !id_ir[10];
smdr[9] = DFFE(smdr[9]_lut_out, clock, reset, , A1L347);


--A1L573 is i~498
--operation mode is normal

A1L573 = A1L473 & (smdr[9] # !select_y[0]) # !A1L473 & reg_B[9] & select_y[0];


--gr[6][9] is gr[6][9]
--operation mode is normal

gr[6][9]_lut_out = reg_C1[9];
gr[6][9] = DFFE(gr[6][9]_lut_out, clock, reset, , A1L461);


--gr[3][9] is gr[3][9]
--operation mode is normal

gr[3][9]_lut_out = reg_C1[9];
gr[3][9] = DFFE(gr[3][9]_lut_out, clock, reset, , A1L011);


--gr[2][9] is gr[2][9]
--operation mode is normal

gr[2][9]_lut_out = reg_C1[9];
gr[2][9] = DFFE(gr[2][9]_lut_out, clock, reset, , A1L29);


--A1L273 is i~495
--operation mode is normal

A1L273 = select_y[0] & (select_y[2] # gr[3][9]) # !select_y[0] & !select_y[2] & gr[2][9];


--gr[7][9] is gr[7][9]
--operation mode is normal

gr[7][9]_lut_out = reg_C1[9];
gr[7][9] = DFFE(gr[7][9]_lut_out, clock, reset, , A1L281);


--A1L373 is i~496
--operation mode is normal

A1L373 = A1L273 & (gr[7][9] # !select_y[2]) # !A1L273 & gr[6][9] & select_y[2];


--gr[4][9] is gr[4][9]
--operation mode is normal

gr[4][9]_lut_out = reg_C1[9];
gr[4][9] = DFFE(gr[4][9]_lut_out, clock, reset, , A1L821);


--gr[1][9] is gr[1][9]
--operation mode is normal

gr[1][9]_lut_out = reg_C1[9];
gr[1][9] = DFFE(gr[1][9]_lut_out, clock, reset, , A1L47);


--zf is zf
--operation mode is normal

zf_lut_out = A1L206 & A1L306 & A1L406 & A1L506;
zf = DFFE(zf_lut_out, clock, reset, , A1L377);


--A1L073 is i~493
--operation mode is normal

A1L073 = select_y[0] & (select_y[2] # gr[1][9]) # !select_y[0] & !select_y[2] & zf;


--gr[5][9] is gr[5][9]
--operation mode is normal

gr[5][9]_lut_out = reg_C1[9];
gr[5][9] = DFFE(gr[5][9]_lut_out, clock, reset, , A1L641);


--A1L173 is i~494
--operation mode is normal

A1L173 = A1L073 & (gr[5][9] # !select_y[2]) # !A1L073 & gr[4][9] & select_y[2];


--A1L863 is i~491
--operation mode is normal

A1L863 = select_y[1] & (select_y[3] # A1L373) # !select_y[1] & !select_y[3] & A1L173;


--id_ir[9] is id_ir[9]
--operation mode is normal

id_ir[9]_lut_out = i_datain[9];
id_ir[9] = DFFE(id_ir[9]_lut_out, clock, reset, , state);


--reg_C[9] is reg_C[9]
--operation mode is normal

reg_C[9]_lut_out = F3_cs_buffer[9];
reg_C[9] = DFFE(reg_C[9]_lut_out, clock, reset, , state);


--A1L575 is i~5973
--operation mode is normal

A1L575 = select_y[0] & reg_C[9] & !select_y[2] # !select_y[0] & id_ir[9] & select_y[2];


--A1L963 is i~492
--operation mode is normal

A1L963 = A1L863 & (A1L575 # !select_y[3]) # !A1L863 & A1L573 & select_y[3];


--reg_C1[8] is reg_C1[8]
--operation mode is normal

reg_C1[8]_lut_out = mem_ir[11] & reg_C[8] # !mem_ir[11] & (A1L785 & reg_C[8] # !A1L785 & d_datain[8]);
reg_C1[8] = DFFE(reg_C1[8]_lut_out, clock, reset, , state);


--reg_B[8] is reg_B[8]
--operation mode is normal

reg_B[8]_lut_out = A1L652 & (A1L115 # A1L982 & A1L172) # !A1L652 & A1L982 & A1L172;
reg_B[8] = DFFE(reg_B[8]_lut_out, clock, reset, , state);


--reg_A[8] is reg_A[8]
--operation mode is normal

reg_A[8]_lut_out = !A1L122;
reg_A[8] = DFFE(reg_A[8]_lut_out, clock, reset, , state);


--A1L283 is i~505
--operation mode is normal

A1L283 = select_y[0] & (select_y[2] # reg_B[8]) # !select_y[0] & !select_y[2] & reg_A[8];


--smdr[8] is smdr[8]
--operation mode is normal

smdr[8]_lut_out = A1L364 & (A1L706 # id_ir[10]) # !A1L364 & A1L706 & !id_ir[10];
smdr[8] = DFFE(smdr[8]_lut_out, clock, reset, , A1L347);


--A1L383 is i~506
--operation mode is normal

A1L383 = A1L283 & (smdr[8] # !select_y[2]) # !A1L283 & reg_C1[8] & select_y[2];


--gr[3][8] is gr[3][8]
--operation mode is normal

gr[3][8]_lut_out = reg_C1[8];
gr[3][8] = DFFE(gr[3][8]_lut_out, clock, reset, , A1L011);


--gr[6][8] is gr[6][8]
--operation mode is normal

gr[6][8]_lut_out = reg_C1[8];
gr[6][8] = DFFE(gr[6][8]_lut_out, clock, reset, , A1L461);


--gr[2][8] is gr[2][8]
--operation mode is normal

gr[2][8]_lut_out = reg_C1[8];
gr[2][8] = DFFE(gr[2][8]_lut_out, clock, reset, , A1L29);


--A1L083 is i~503
--operation mode is normal

A1L083 = select_y[2] & (select_y[0] # gr[6][8]) # !select_y[2] & !select_y[0] & gr[2][8];


--gr[7][8] is gr[7][8]
--operation mode is normal

gr[7][8]_lut_out = reg_C1[8];
gr[7][8] = DFFE(gr[7][8]_lut_out, clock, reset, , A1L281);


--A1L183 is i~504
--operation mode is normal

A1L183 = A1L083 & (gr[7][8] # !select_y[0]) # !A1L083 & gr[3][8] & select_y[0];


--gr[4][8] is gr[4][8]
--operation mode is normal

gr[4][8]_lut_out = reg_C1[8];
gr[4][8] = DFFE(gr[4][8]_lut_out, clock, reset, , A1L821);


--gr[1][8] is gr[1][8]
--operation mode is normal

gr[1][8]_lut_out = reg_C1[8];
gr[1][8] = DFFE(gr[1][8]_lut_out, clock, reset, , A1L47);


--nf is nf
--operation mode is normal

nf_lut_out = D1_unreg_res_node[15];
nf = DFFE(nf_lut_out, clock, reset, , A1L377);


--A1L873 is i~501
--operation mode is normal

A1L873 = select_y[0] & (select_y[2] # gr[1][8]) # !select_y[0] & !select_y[2] & nf;


--gr[5][8] is gr[5][8]
--operation mode is normal

gr[5][8]_lut_out = reg_C1[8];
gr[5][8] = DFFE(gr[5][8]_lut_out, clock, reset, , A1L641);


--A1L973 is i~502
--operation mode is normal

A1L973 = A1L873 & (gr[5][8] # !select_y[2]) # !A1L873 & gr[4][8] & select_y[2];


--A1L673 is i~499
--operation mode is normal

A1L673 = select_y[1] & (select_y[3] # A1L183) # !select_y[1] & !select_y[3] & A1L973;


--id_ir[8] is id_ir[8]
--operation mode is normal

id_ir[8]_lut_out = i_datain[8];
id_ir[8] = DFFE(id_ir[8]_lut_out, clock, reset, , state);


--reg_C[8] is reg_C[8]
--operation mode is normal

reg_C[8]_lut_out = F3_cs_buffer[8];
reg_C[8] = DFFE(reg_C[8]_lut_out, clock, reset, , state);


--A1L675 is i~5974
--operation mode is normal

A1L675 = select_y[0] & reg_C[8] & !select_y[2] # !select_y[0] & id_ir[8] & select_y[2];


--A1L773 is i~500
--operation mode is normal

A1L773 = A1L673 & (A1L675 # !select_y[3]) # !A1L673 & A1L383 & select_y[3];


--reg_B[7] is reg_B[7]
--operation mode is normal

reg_B[7]_lut_out = A1L372 # A1L472 # A1L652 & A1L515;
reg_B[7] = DFFE(reg_B[7]_lut_out, clock, reset, , state);


--reg_C1[7] is reg_C1[7]
--operation mode is normal

reg_C1[7]_lut_out = mem_ir[11] & reg_C[7] # !mem_ir[11] & (A1L785 & reg_C[7] # !A1L785 & d_datain[7]);
reg_C1[7] = DFFE(reg_C1[7]_lut_out, clock, reset, , state);


--reg_A[7] is reg_A[7]
--operation mode is normal

reg_A[7]_lut_out = !A1L522;
reg_A[7] = DFFE(reg_A[7]_lut_out, clock, reset, , state);


--A1L093 is i~513
--operation mode is normal

A1L093 = select_y[2] & (select_y[0] # reg_C1[7]) # !select_y[2] & !select_y[0] & reg_A[7];


--smdr[7] is smdr[7]
--operation mode is normal

smdr[7]_lut_out = A1L564 & (A1L906 # id_ir[10]) # !A1L564 & A1L906 & !id_ir[10];
smdr[7] = DFFE(smdr[7]_lut_out, clock, reset, , A1L347);


--A1L193 is i~514
--operation mode is normal

A1L193 = A1L093 & (smdr[7] # !select_y[0]) # !A1L093 & reg_B[7] & select_y[0];


--gr[6][7] is gr[6][7]
--operation mode is normal

gr[6][7]_lut_out = reg_C1[7];
gr[6][7] = DFFE(gr[6][7]_lut_out, clock, reset, , A1L461);


--gr[3][7] is gr[3][7]
--operation mode is normal

gr[3][7]_lut_out = reg_C1[7];
gr[3][7] = DFFE(gr[3][7]_lut_out, clock, reset, , A1L011);


--gr[2][7] is gr[2][7]
--operation mode is normal

gr[2][7]_lut_out = reg_C1[7];
gr[2][7] = DFFE(gr[2][7]_lut_out, clock, reset, , A1L29);


--A1L883 is i~511
--operation mode is normal

A1L883 = select_y[0] & (select_y[2] # gr[3][7]) # !select_y[0] & !select_y[2] & gr[2][7];


--gr[7][7] is gr[7][7]
--operation mode is normal

gr[7][7]_lut_out = reg_C1[7];
gr[7][7] = DFFE(gr[7][7]_lut_out, clock, reset, , A1L281);


--A1L983 is i~512
--operation mode is normal

A1L983 = A1L883 & (gr[7][7] # !select_y[2]) # !A1L883 & gr[6][7] & select_y[2];


--gr[1][7] is gr[1][7]
--operation mode is normal

gr[1][7]_lut_out = reg_C1[7];
gr[1][7] = DFFE(gr[1][7]_lut_out, clock, reset, , A1L47);


--gr[4][7] is gr[4][7]
--operation mode is normal

gr[4][7]_lut_out = reg_C1[7];
gr[4][7] = DFFE(gr[4][7]_lut_out, clock, reset, , A1L821);


--A1L683 is i~509
--operation mode is normal

A1L683 = select_y[2] & (select_y[0] # gr[4][7]) # !select_y[2] & !select_y[0] & G1_q[7];


--gr[5][7] is gr[5][7]
--operation mode is normal

gr[5][7]_lut_out = reg_C1[7];
gr[5][7] = DFFE(gr[5][7]_lut_out, clock, reset, , A1L641);


--A1L783 is i~510
--operation mode is normal

A1L783 = A1L683 & (gr[5][7] # !select_y[0]) # !A1L683 & gr[1][7] & select_y[0];


--A1L483 is i~507
--operation mode is normal

A1L483 = select_y[1] & (select_y[3] # A1L983) # !select_y[1] & !select_y[3] & A1L783;


--id_ir[7] is id_ir[7]
--operation mode is normal

id_ir[7]_lut_out = i_datain[7];
id_ir[7] = DFFE(id_ir[7]_lut_out, clock, reset, , state);


--A1L775 is i~5975
--operation mode is normal

A1L775 = select_y[0] & reg_C[7] & !select_y[2] # !select_y[0] & id_ir[7] & select_y[2];


--A1L583 is i~508
--operation mode is normal

A1L583 = A1L483 & (A1L775 # !select_y[3]) # !A1L483 & A1L193 & select_y[3];


--reg_C1[6] is reg_C1[6]
--operation mode is normal

reg_C1[6]_lut_out = mem_ir[11] & reg_C[6] # !mem_ir[11] & (A1L785 & reg_C[6] # !A1L785 & d_datain[6]);
reg_C1[6] = DFFE(reg_C1[6]_lut_out, clock, reset, , state);


--reg_B[6] is reg_B[6]
--operation mode is normal

reg_B[6]_lut_out = A1L672 # A1L772 # A1L652 & A1L915;
reg_B[6] = DFFE(reg_B[6]_lut_out, clock, reset, , state);


--reg_A[6] is reg_A[6]
--operation mode is normal

reg_A[6]_lut_out = !A1L922;
reg_A[6] = DFFE(reg_A[6]_lut_out, clock, reset, , state);


--A1L893 is i~521
--operation mode is normal

A1L893 = select_y[0] & (select_y[2] # reg_B[6]) # !select_y[0] & !select_y[2] & reg_A[6];


--smdr[6] is smdr[6]
--operation mode is normal

smdr[6]_lut_out = A1L764 & (A1L116 # id_ir[10]) # !A1L764 & A1L116 & !id_ir[10];