smdr[6] = DFFE(smdr[6]_lut_out, clock, reset, , A1L347);


--A1L993 is i~522
--operation mode is normal

A1L993 = A1L893 & (smdr[6] # !select_y[2]) # !A1L893 & reg_C1[6] & select_y[2];


--gr[3][6] is gr[3][6]
--operation mode is normal

gr[3][6]_lut_out = reg_C1[6];
gr[3][6] = DFFE(gr[3][6]_lut_out, clock, reset, , A1L011);


--gr[6][6] is gr[6][6]
--operation mode is normal

gr[6][6]_lut_out = reg_C1[6];
gr[6][6] = DFFE(gr[6][6]_lut_out, clock, reset, , A1L461);


--gr[2][6] is gr[2][6]
--operation mode is normal

gr[2][6]_lut_out = reg_C1[6];
gr[2][6] = DFFE(gr[2][6]_lut_out, clock, reset, , A1L29);


--A1L693 is i~519
--operation mode is normal

A1L693 = select_y[2] & (select_y[0] # gr[6][6]) # !select_y[2] & !select_y[0] & gr[2][6];


--gr[7][6] is gr[7][6]
--operation mode is normal

gr[7][6]_lut_out = reg_C1[6];
gr[7][6] = DFFE(gr[7][6]_lut_out, clock, reset, , A1L281);


--A1L793 is i~520
--operation mode is normal

A1L793 = A1L693 & (gr[7][6] # !select_y[0]) # !A1L693 & gr[3][6] & select_y[0];


--gr[4][6] is gr[4][6]
--operation mode is normal

gr[4][6]_lut_out = reg_C1[6];
gr[4][6] = DFFE(gr[4][6]_lut_out, clock, reset, , A1L821);


--gr[1][6] is gr[1][6]
--operation mode is normal

gr[1][6]_lut_out = reg_C1[6];
gr[1][6] = DFFE(gr[1][6]_lut_out, clock, reset, , A1L47);


--A1L493 is i~517
--operation mode is normal

A1L493 = select_y[0] & (select_y[2] # gr[1][6]) # !select_y[0] & !select_y[2] & G1_q[6];


--gr[5][6] is gr[5][6]
--operation mode is normal

gr[5][6]_lut_out = reg_C1[6];
gr[5][6] = DFFE(gr[5][6]_lut_out, clock, reset, , A1L641);


--A1L593 is i~518
--operation mode is normal

A1L593 = A1L493 & (gr[5][6] # !select_y[2]) # !A1L493 & gr[4][6] & select_y[2];


--A1L293 is i~515
--operation mode is normal

A1L293 = select_y[1] & (select_y[3] # A1L793) # !select_y[1] & !select_y[3] & A1L593;


--id_ir[6] is id_ir[6]
--operation mode is normal

id_ir[6]_lut_out = i_datain[6];
id_ir[6] = DFFE(id_ir[6]_lut_out, clock, reset, , state);


--A1L875 is i~5976
--operation mode is normal

A1L875 = select_y[0] & reg_C[6] & !select_y[2] # !select_y[0] & id_ir[6] & select_y[2];


--A1L393 is i~516
--operation mode is normal

A1L393 = A1L293 & (A1L875 # !select_y[3]) # !A1L293 & A1L993 & select_y[3];


--reg_B[5] is reg_B[5]
--operation mode is normal

reg_B[5]_lut_out = A1L972 # A1L082 # A1L652 & A1L325;
reg_B[5] = DFFE(reg_B[5]_lut_out, clock, reset, , state);


--reg_C1[5] is reg_C1[5]
--operation mode is normal

reg_C1[5]_lut_out = mem_ir[11] & reg_C[5] # !mem_ir[11] & (A1L785 & reg_C[5] # !A1L785 & d_datain[5]);
reg_C1[5] = DFFE(reg_C1[5]_lut_out, clock, reset, , state);


--reg_A[5] is reg_A[5]
--operation mode is normal

reg_A[5]_lut_out = !A1L332;
reg_A[5] = DFFE(reg_A[5]_lut_out, clock, reset, , state);


--A1L604 is i~529
--operation mode is normal

A1L604 = select_y[2] & (select_y[0] # reg_C1[5]) # !select_y[2] & !select_y[0] & reg_A[5];


--smdr[5] is smdr[5]
--operation mode is normal

smdr[5]_lut_out = A1L964 & (A1L316 # id_ir[10]) # !A1L964 & A1L316 & !id_ir[10];
smdr[5] = DFFE(smdr[5]_lut_out, clock, reset, , A1L347);


--A1L704 is i~530
--operation mode is normal

A1L704 = A1L604 & (smdr[5] # !select_y[0]) # !A1L604 & reg_B[5] & select_y[0];


--gr[6][5] is gr[6][5]
--operation mode is normal

gr[6][5]_lut_out = reg_C1[5];
gr[6][5] = DFFE(gr[6][5]_lut_out, clock, reset, , A1L461);


--gr[3][5] is gr[3][5]
--operation mode is normal

gr[3][5]_lut_out = reg_C1[5];
gr[3][5] = DFFE(gr[3][5]_lut_out, clock, reset, , A1L011);


--gr[2][5] is gr[2][5]
--operation mode is normal

gr[2][5]_lut_out = reg_C1[5];
gr[2][5] = DFFE(gr[2][5]_lut_out, clock, reset, , A1L29);


--A1L404 is i~527
--operation mode is normal

A1L404 = select_y[0] & (select_y[2] # gr[3][5]) # !select_y[0] & !select_y[2] & gr[2][5];


--gr[7][5] is gr[7][5]
--operation mode is normal

gr[7][5]_lut_out = reg_C1[5];
gr[7][5] = DFFE(gr[7][5]_lut_out, clock, reset, , A1L281);


--A1L504 is i~528
--operation mode is normal

A1L504 = A1L404 & (gr[7][5] # !select_y[2]) # !A1L404 & gr[6][5] & select_y[2];


--gr[1][5] is gr[1][5]
--operation mode is normal

gr[1][5]_lut_out = reg_C1[5];
gr[1][5] = DFFE(gr[1][5]_lut_out, clock, reset, , A1L47);


--gr[4][5] is gr[4][5]
--operation mode is normal

gr[4][5]_lut_out = reg_C1[5];
gr[4][5] = DFFE(gr[4][5]_lut_out, clock, reset, , A1L821);


--A1L204 is i~525
--operation mode is normal

A1L204 = select_y[2] & (select_y[0] # gr[4][5]) # !select_y[2] & !select_y[0] & G1_q[5];


--gr[5][5] is gr[5][5]
--operation mode is normal

gr[5][5]_lut_out = reg_C1[5];
gr[5][5] = DFFE(gr[5][5]_lut_out, clock, reset, , A1L641);


--A1L304 is i~526
--operation mode is normal

A1L304 = A1L204 & (gr[5][5] # !select_y[0]) # !A1L204 & gr[1][5] & select_y[0];


--A1L004 is i~523
--operation mode is normal

A1L004 = select_y[1] & (select_y[3] # A1L504) # !select_y[1] & !select_y[3] & A1L304;


--id_ir[5] is id_ir[5]
--operation mode is normal

id_ir[5]_lut_out = i_datain[5];
id_ir[5] = DFFE(id_ir[5]_lut_out, clock, reset, , state);


--A1L975 is i~5977
--operation mode is normal

A1L975 = select_y[0] & reg_C[5] & !select_y[2] # !select_y[0] & id_ir[5] & select_y[2];


--A1L104 is i~524
--operation mode is normal

A1L104 = A1L004 & (A1L975 # !select_y[3]) # !A1L004 & A1L704 & select_y[3];


--reg_C1[4] is reg_C1[4]
--operation mode is normal

reg_C1[4]_lut_out = mem_ir[11] & reg_C[4] # !mem_ir[11] & (A1L785 & reg_C[4] # !A1L785 & d_datain[4]);
reg_C1[4] = DFFE(reg_C1[4]_lut_out, clock, reset, , state);


--reg_B[4] is reg_B[4]
--operation mode is normal

reg_B[4]_lut_out = A1L282 # A1L382 # A1L652 & A1L725;
reg_B[4] = DFFE(reg_B[4]_lut_out, clock, reset, , state);


--reg_A[4] is reg_A[4]
--operation mode is normal

reg_A[4]_lut_out = !A1L732;
reg_A[4] = DFFE(reg_A[4]_lut_out, clock, reset, , state);


--A1L414 is i~537
--operation mode is normal

A1L414 = select_y[0] & (select_y[2] # reg_B[4]) # !select_y[0] & !select_y[2] & reg_A[4];


--smdr[4] is smdr[4]
--operation mode is normal

smdr[4]_lut_out = A1L174 & (A1L516 # id_ir[10]) # !A1L174 & A1L516 & !id_ir[10];
smdr[4] = DFFE(smdr[4]_lut_out, clock, reset, , A1L347);


--A1L514 is i~538
--operation mode is normal

A1L514 = A1L414 & (smdr[4] # !select_y[2]) # !A1L414 & reg_C1[4] & select_y[2];


--gr[3][4] is gr[3][4]
--operation mode is normal

gr[3][4]_lut_out = reg_C1[4];
gr[3][4] = DFFE(gr[3][4]_lut_out, clock, reset, , A1L011);


--gr[6][4] is gr[6][4]
--operation mode is normal

gr[6][4]_lut_out = reg_C1[4];
gr[6][4] = DFFE(gr[6][4]_lut_out, clock, reset, , A1L461);


--gr[2][4] is gr[2][4]
--operation mode is normal

gr[2][4]_lut_out = reg_C1[4];
gr[2][4] = DFFE(gr[2][4]_lut_out, clock, reset, , A1L29);


--A1L214 is i~535
--operation mode is normal

A1L214 = select_y[2] & (select_y[0] # gr[6][4]) # !select_y[2] & !select_y[0] & gr[2][4];


--gr[7][4] is gr[7][4]
--operation mode is normal

gr[7][4]_lut_out = reg_C1[4];
gr[7][4] = DFFE(gr[7][4]_lut_out, clock, reset, , A1L281);


--A1L314 is i~536
--operation mode is normal

A1L314 = A1L214 & (gr[7][4] # !select_y[0]) # !A1L214 & gr[3][4] & select_y[0];


--gr[4][4] is gr[4][4]
--operation mode is normal

gr[4][4]_lut_out = reg_C1[4];
gr[4][4] = DFFE(gr[4][4]_lut_out, clock, reset, , A1L821);


--gr[1][4] is gr[1][4]
--operation mode is normal

gr[1][4]_lut_out = reg_C1[4];
gr[1][4] = DFFE(gr[1][4]_lut_out, clock, reset, , A1L47);


--A1L014 is i~533
--operation mode is normal

A1L014 = select_y[0] & (select_y[2] # gr[1][4]) # !select_y[0] & !select_y[2] & G1_q[4];


--gr[5][4] is gr[5][4]
--operation mode is normal

gr[5][4]_lut_out = reg_C1[4];
gr[5][4] = DFFE(gr[5][4]_lut_out, clock, reset, , A1L641);


--A1L114 is i~534
--operation mode is normal

A1L114 = A1L014 & (gr[5][4] # !select_y[2]) # !A1L014 & gr[4][4] & select_y[2];


--A1L804 is i~531
--operation mode is normal

A1L804 = select_y[1] & (select_y[3] # A1L314) # !select_y[1] & !select_y[3] & A1L114;


--id_ir[4] is id_ir[4]
--operation mode is normal

id_ir[4]_lut_out = i_datain[4];
id_ir[4] = DFFE(id_ir[4]_lut_out, clock, reset, , state);


--A1L085 is i~5978
--operation mode is normal

A1L085 = select_y[0] & reg_C[4] & !select_y[2] # !select_y[0] & id_ir[4] & select_y[2];


--A1L904 is i~532
--operation mode is normal

A1L904 = A1L804 & (A1L085 # !select_y[3]) # !A1L804 & A1L514 & select_y[3];


--reg_B[3] is reg_B[3]
--operation mode is normal

reg_B[3]_lut_out = A1L682 # id_ir[3] & (A1L881 # A1L685);
reg_B[3] = DFFE(reg_B[3]_lut_out, clock, reset, , state);


--reg_C1[3] is reg_C1[3]
--operation mode is normal

reg_C1[3]_lut_out = mem_ir[11] & reg_C[3] # !mem_ir[11] & (A1L785 & reg_C[3] # !A1L785 & d_datain[3]);
reg_C1[3] = DFFE(reg_C1[3]_lut_out, clock, reset, , state);


--reg_A[3] is reg_A[3]
--operation mode is normal

reg_A[3]_lut_out = !A1L142;
reg_A[3] = DFFE(reg_A[3]_lut_out, clock, reset, , state);


--A1L224 is i~545
--operation mode is normal

A1L224 = select_y[2] & (select_y[0] # reg_C1[3]) # !select_y[2] & !select_y[0] & reg_A[3];


--smdr[3] is smdr[3]
--operation mode is normal

smdr[3]_lut_out = A1L374 & (A1L716 # id_ir[10]) # !A1L374 & A1L716 & !id_ir[10];
smdr[3] = DFFE(smdr[3]_lut_out, clock, reset, , A1L347);


--A1L324 is i~546
--operation mode is normal

A1L324 = A1L224 & (smdr[3] # !select_y[0]) # !A1L224 & reg_B[3] & select_y[0];


--gr[6][3] is gr[6][3]
--operation mode is normal

gr[6][3]_lut_out = reg_C1[3];
gr[6][3] = DFFE(gr[6][3]_lut_out, clock, reset, , A1L461);


--gr[3][3] is gr[3][3]
--operation mode is normal

gr[3][3]_lut_out = reg_C1[3];
gr[3][3] = DFFE(gr[3][3]_lut_out, clock, reset, , A1L011);


--gr[2][3] is gr[2][3]
--operation mode is normal

gr[2][3]_lut_out = reg_C1[3];
gr[2][3] = DFFE(gr[2][3]_lut_out, clock, reset, , A1L29);


--A1L024 is i~543
--operation mode is normal

A1L024 = select_y[0] & (select_y[2] # gr[3][3]) # !select_y[0] & !select_y[2] & gr[2][3];


--gr[7][3] is gr[7][3]
--operation mode is normal

gr[7][3]_lut_out = reg_C1[3];
gr[7][3] = DFFE(gr[7][3]_lut_out, clock, reset, , A1L281);


--A1L124 is i~544
--operation mode is normal

A1L124 = A1L024 & (gr[7][3] # !select_y[2]) # !A1L024 & gr[6][3] & select_y[2];


--gr[1][3] is gr[1][3]
--operation mode is normal

gr[1][3]_lut_out = reg_C1[3];
gr[1][3] = DFFE(gr[1][3]_lut_out, clock, reset, , A1L47);


--gr[4][3] is gr[4][3]
--operation mode is normal

gr[4][3]_lut_out = reg_C1[3];
gr[4][3] = DFFE(gr[4][3]_lut_out, clock, reset, , A1L821);


--A1L814 is i~541
--operation mode is normal

A1L814 = select_y[2] & (select_y[0] # gr[4][3]) # !select_y[2] & !select_y[0] & G1_q[3];


--gr[5][3] is gr[5][3]
--operation mode is normal

gr[5][3]_lut_out = reg_C1[3];
gr[5][3] = DFFE(gr[5][3]_lut_out, clock, reset, , A1L641);


--A1L914 is i~542
--operation mode is normal

A1L914 = A1L814 & (gr[5][3] # !select_y[0]) # !A1L814 & gr[1][3] & select_y[0];


--A1L614 is i~539
--operation mode is normal

A1L614 = select_y[1] & (select_y[3] # A1L124) # !select_y[1] & !select_y[3] & A1L914;


--id_ir[3] is id_ir[3]
--operation mode is normal

id_ir[3]_lut_out = i_datain[3];
id_ir[3] = DFFE(id_ir[3]_lut_out, clock, reset, , state);


--A1L185 is i~5979
--operation mode is normal

A1L185 = select_y[0] & reg_C[3] & !select_y[2] # !select_y[0] & id_ir[3] & select_y[2];


--A1L714 is i~540
--operation mode is normal

A1L714 = A1L614 & (A1L185 # !select_y[3]) # !A1L614 & A1L324 & select_y[3];


--reg_C1[2] is reg_C1[2]
--operation mode is normal

reg_C1[2]_lut_out = mem_ir[11] & reg_C[2] # !mem_ir[11] & (A1L785 & reg_C[2] # !A1L785 & d_datain[2]);
reg_C1[2] = DFFE(reg_C1[2]_lut_out, clock, reset, , state);


--reg_B[2] is reg_B[2]
--operation mode is normal

reg_B[2]_lut_out = id_ir[2] & (A1L535 # !A1L752) # !id_ir[2] & A1L882 & A1L752;
reg_B[2] = DFFE(reg_B[2]_lut_out, clock, reset, , state);


--reg_A[2] is reg_A[2]
--operation mode is normal

reg_A[2]_lut_out = !A1L542;
reg_A[2] = DFFE(reg_A[2]_lut_out, clock, reset, , state);


--A1L034 is i~553
--operation mode is normal

A1L034 = select_y[0] & (select_y[2] # reg_B[2]) # !select_y[0] & !select_y[2] & reg_A[2];


--smdr[2] is smdr[2]