--operation mode is normal

smdr[2]_lut_out = A1L574 & (A1L916 # id_ir[10]) # !A1L574 & A1L916 & !id_ir[10];
smdr[2] = DFFE(smdr[2]_lut_out, clock, reset, , A1L347);


--A1L134 is i~554
--operation mode is normal

A1L134 = A1L034 & (smdr[2] # !select_y[2]) # !A1L034 & reg_C1[2] & select_y[2];


--gr[3][2] is gr[3][2]
--operation mode is normal

gr[3][2]_lut_out = reg_C1[2];
gr[3][2] = DFFE(gr[3][2]_lut_out, clock, reset, , A1L011);


--gr[6][2] is gr[6][2]
--operation mode is normal

gr[6][2]_lut_out = reg_C1[2];
gr[6][2] = DFFE(gr[6][2]_lut_out, clock, reset, , A1L461);


--gr[2][2] is gr[2][2]
--operation mode is normal

gr[2][2]_lut_out = reg_C1[2];
gr[2][2] = DFFE(gr[2][2]_lut_out, clock, reset, , A1L29);


--A1L824 is i~551
--operation mode is normal

A1L824 = select_y[2] & (select_y[0] # gr[6][2]) # !select_y[2] & !select_y[0] & gr[2][2];


--gr[7][2] is gr[7][2]
--operation mode is normal

gr[7][2]_lut_out = reg_C1[2];
gr[7][2] = DFFE(gr[7][2]_lut_out, clock, reset, , A1L281);


--A1L924 is i~552
--operation mode is normal

A1L924 = A1L824 & (gr[7][2] # !select_y[0]) # !A1L824 & gr[3][2] & select_y[0];


--gr[4][2] is gr[4][2]
--operation mode is normal

gr[4][2]_lut_out = reg_C1[2];
gr[4][2] = DFFE(gr[4][2]_lut_out, clock, reset, , A1L821);


--gr[1][2] is gr[1][2]
--operation mode is normal

gr[1][2]_lut_out = reg_C1[2];
gr[1][2] = DFFE(gr[1][2]_lut_out, clock, reset, , A1L47);


--A1L624 is i~549
--operation mode is normal

A1L624 = select_y[0] & (select_y[2] # gr[1][2]) # !select_y[0] & !select_y[2] & G1_q[2];


--gr[5][2] is gr[5][2]
--operation mode is normal

gr[5][2]_lut_out = reg_C1[2];
gr[5][2] = DFFE(gr[5][2]_lut_out, clock, reset, , A1L641);


--A1L724 is i~550
--operation mode is normal

A1L724 = A1L624 & (gr[5][2] # !select_y[2]) # !A1L624 & gr[4][2] & select_y[2];


--A1L424 is i~547
--operation mode is normal

A1L424 = select_y[1] & (select_y[3] # A1L924) # !select_y[1] & !select_y[3] & A1L724;


--id_ir[2] is id_ir[2]
--operation mode is normal

id_ir[2]_lut_out = i_datain[2];
id_ir[2] = DFFE(id_ir[2]_lut_out, clock, reset, , state);


--A1L285 is i~5980
--operation mode is normal

A1L285 = select_y[0] & reg_C[2] & !select_y[2] # !select_y[0] & id_ir[2] & select_y[2];


--A1L524 is i~548
--operation mode is normal

A1L524 = A1L424 & (A1L285 # !select_y[3]) # !A1L424 & A1L134 & select_y[3];


--reg_B[1] is reg_B[1]
--operation mode is normal

reg_B[1]_lut_out = A1L192 # id_ir[1] & (A1L292 # !A1L752);
reg_B[1] = DFFE(reg_B[1]_lut_out, clock, reset, , state);


--reg_C1[1] is reg_C1[1]
--operation mode is normal

reg_C1[1]_lut_out = mem_ir[11] & reg_C[1] # !mem_ir[11] & (A1L785 & reg_C[1] # !A1L785 & d_datain[1]);
reg_C1[1] = DFFE(reg_C1[1]_lut_out, clock, reset, , state);


--reg_A[1] is reg_A[1]
--operation mode is normal

reg_A[1]_lut_out = !A1L942;
reg_A[1] = DFFE(reg_A[1]_lut_out, clock, reset, , state);


--A1L834 is i~561
--operation mode is normal

A1L834 = select_y[2] & (select_y[0] # reg_C1[1]) # !select_y[2] & !select_y[0] & reg_A[1];


--smdr[1] is smdr[1]
--operation mode is normal

smdr[1]_lut_out = A1L774 & (A1L126 # id_ir[10]) # !A1L774 & A1L126 & !id_ir[10];
smdr[1] = DFFE(smdr[1]_lut_out, clock, reset, , A1L347);


--A1L934 is i~562
--operation mode is normal

A1L934 = A1L834 & (smdr[1] # !select_y[0]) # !A1L834 & reg_B[1] & select_y[0];


--gr[6][1] is gr[6][1]
--operation mode is normal

gr[6][1]_lut_out = reg_C1[1];
gr[6][1] = DFFE(gr[6][1]_lut_out, clock, reset, , A1L461);


--gr[3][1] is gr[3][1]
--operation mode is normal

gr[3][1]_lut_out = reg_C1[1];
gr[3][1] = DFFE(gr[3][1]_lut_out, clock, reset, , A1L011);


--gr[2][1] is gr[2][1]
--operation mode is normal

gr[2][1]_lut_out = reg_C1[1];
gr[2][1] = DFFE(gr[2][1]_lut_out, clock, reset, , A1L29);


--A1L634 is i~559
--operation mode is normal

A1L634 = select_y[0] & (select_y[2] # gr[3][1]) # !select_y[0] & !select_y[2] & gr[2][1];


--gr[7][1] is gr[7][1]
--operation mode is normal

gr[7][1]_lut_out = reg_C1[1];
gr[7][1] = DFFE(gr[7][1]_lut_out, clock, reset, , A1L281);


--A1L734 is i~560
--operation mode is normal

A1L734 = A1L634 & (gr[7][1] # !select_y[2]) # !A1L634 & gr[6][1] & select_y[2];


--gr[1][1] is gr[1][1]
--operation mode is normal

gr[1][1]_lut_out = reg_C1[1];
gr[1][1] = DFFE(gr[1][1]_lut_out, clock, reset, , A1L47);


--gr[4][1] is gr[4][1]
--operation mode is normal

gr[4][1]_lut_out = reg_C1[1];
gr[4][1] = DFFE(gr[4][1]_lut_out, clock, reset, , A1L821);


--A1L434 is i~557
--operation mode is normal

A1L434 = select_y[2] & (select_y[0] # gr[4][1]) # !select_y[2] & !select_y[0] & G1_q[1];


--gr[5][1] is gr[5][1]
--operation mode is normal

gr[5][1]_lut_out = reg_C1[1];
gr[5][1] = DFFE(gr[5][1]_lut_out, clock, reset, , A1L641);


--A1L534 is i~558
--operation mode is normal

A1L534 = A1L434 & (gr[5][1] # !select_y[0]) # !A1L434 & gr[1][1] & select_y[0];


--A1L234 is i~555
--operation mode is normal

A1L234 = select_y[1] & (select_y[3] # A1L734) # !select_y[1] & !select_y[3] & A1L534;


--id_ir[1] is id_ir[1]
--operation mode is normal

id_ir[1]_lut_out = i_datain[1];
id_ir[1] = DFFE(id_ir[1]_lut_out, clock, reset, , state);


--A1L385 is i~5981
--operation mode is normal

A1L385 = select_y[0] & reg_C[1] & !select_y[2] # !select_y[0] & id_ir[1] & select_y[2];


--A1L334 is i~556
--operation mode is normal

A1L334 = A1L234 & (A1L385 # !select_y[3]) # !A1L234 & A1L934 & select_y[3];


--reg_C1[0] is reg_C1[0]
--operation mode is normal

reg_C1[0]_lut_out = mem_ir[11] & reg_C[0] # !mem_ir[11] & (A1L785 & reg_C[0] # !A1L785 & d_datain[0]);
reg_C1[0] = DFFE(reg_C1[0]_lut_out, clock, reset, , state);


--reg_B[0] is reg_B[0]
--operation mode is normal

reg_B[0]_lut_out = A1L592 # id_ir[0] & (A1L692 # !A1L752);
reg_B[0] = DFFE(reg_B[0]_lut_out, clock, reset, , state);


--reg_A[0] is reg_A[0]
--operation mode is normal

reg_A[0]_lut_out = !A1L352;
reg_A[0] = DFFE(reg_A[0]_lut_out, clock, reset, , state);


--A1L644 is i~569
--operation mode is normal

A1L644 = select_y[0] & (select_y[2] # reg_B[0]) # !select_y[0] & !select_y[2] & reg_A[0];


--smdr[0] is smdr[0]
--operation mode is normal

smdr[0]_lut_out = A1L974 & (A1L326 # id_ir[10]) # !A1L974 & A1L326 & !id_ir[10];
smdr[0] = DFFE(smdr[0]_lut_out, clock, reset, , A1L347);


--A1L744 is i~570
--operation mode is normal

A1L744 = A1L644 & (smdr[0] # !select_y[2]) # !A1L644 & reg_C1[0] & select_y[2];


--gr[3][0] is gr[3][0]
--operation mode is normal

gr[3][0]_lut_out = reg_C1[0];
gr[3][0] = DFFE(gr[3][0]_lut_out, clock, reset, , A1L011);


--gr[6][0] is gr[6][0]
--operation mode is normal

gr[6][0]_lut_out = reg_C1[0];
gr[6][0] = DFFE(gr[6][0]_lut_out, clock, reset, , A1L461);


--gr[2][0] is gr[2][0]
--operation mode is normal

gr[2][0]_lut_out = reg_C1[0];
gr[2][0] = DFFE(gr[2][0]_lut_out, clock, reset, , A1L29);


--A1L444 is i~567
--operation mode is normal

A1L444 = select_y[2] & (select_y[0] # gr[6][0]) # !select_y[2] & !select_y[0] & gr[2][0];


--gr[7][0] is gr[7][0]
--operation mode is normal

gr[7][0]_lut_out = reg_C1[0];
gr[7][0] = DFFE(gr[7][0]_lut_out, clock, reset, , A1L281);


--A1L544 is i~568
--operation mode is normal

A1L544 = A1L444 & (gr[7][0] # !select_y[0]) # !A1L444 & gr[3][0] & select_y[0];


--gr[4][0] is gr[4][0]
--operation mode is normal

gr[4][0]_lut_out = reg_C1[0];
gr[4][0] = DFFE(gr[4][0]_lut_out, clock, reset, , A1L821);


--gr[1][0] is gr[1][0]
--operation mode is normal

gr[1][0]_lut_out = reg_C1[0];
gr[1][0] = DFFE(gr[1][0]_lut_out, clock, reset, , A1L47);


--A1L244 is i~565
--operation mode is normal

A1L244 = select_y[0] & (select_y[2] # gr[1][0]) # !select_y[0] & !select_y[2] & G1_q[0];


--gr[5][0] is gr[5][0]
--operation mode is normal

gr[5][0]_lut_out = reg_C1[0];
gr[5][0] = DFFE(gr[5][0]_lut_out, clock, reset, , A1L641);


--A1L344 is i~566
--operation mode is normal

A1L344 = A1L244 & (gr[5][0] # !select_y[2]) # !A1L244 & gr[4][0] & select_y[2];


--A1L044 is i~563
--operation mode is normal

A1L044 = select_y[1] & (select_y[3] # A1L544) # !select_y[1] & !select_y[3] & A1L344;


--id_ir[0] is id_ir[0]
--operation mode is normal

id_ir[0]_lut_out = i_datain[0];
id_ir[0] = DFFE(id_ir[0]_lut_out, clock, reset, , state);


--A1L485 is i~5982
--operation mode is normal

A1L485 = select_y[0] & reg_C[0] & !select_y[2] # !select_y[0] & id_ir[0] & select_y[2];


--A1L144 is i~564
--operation mode is normal

A1L144 = A1L044 & (A1L485 # !select_y[3]) # !A1L044 & A1L744 & select_y[3];


--state is state
--operation mode is normal

state_lut_out = !A1L581 & enable & (state # start);
state = DFFE(state_lut_out, clock, reset, , );


--mem_ir[13] is mem_ir[13]
--operation mode is normal

mem_ir[13]_lut_out = ex_ir[13];
mem_ir[13] = DFFE(mem_ir[13]_lut_out, clock, reset, , state);


--mem_ir[12] is mem_ir[12]
--operation mode is normal

mem_ir[12]_lut_out = ex_ir[12];
mem_ir[12] = DFFE(mem_ir[12]_lut_out, clock, reset, , state);


--A1L681 is i66~69
--operation mode is normal

A1L681 = mem_ir[13] & nf & !mem_ir[12] # !mem_ir[13] & zf & mem_ir[12];


--mem_ir[15] is mem_ir[15]
--operation mode is normal

mem_ir[15]_lut_out = ex_ir[15];
mem_ir[15] = DFFE(mem_ir[15]_lut_out, clock, reset, , state);


--mem_ir[14] is mem_ir[14]
--operation mode is normal

mem_ir[14]_lut_out = ex_ir[14];
mem_ir[14] = DFFE(mem_ir[14]_lut_out, clock, reset, , state);


--mem_ir[11] is mem_ir[11]
--operation mode is normal

mem_ir[11]_lut_out = ex_ir[11];
mem_ir[11] = DFFE(mem_ir[11]_lut_out, clock, reset, , state);


--A1L781 is i66~70
--operation mode is normal

A1L781 = A1L681 & mem_ir[15] & mem_ir[14] & !mem_ir[11];


--F3_cs_buffer[7] is lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]
--operation mode is arithmetic

F3_cs_buffer[7] = reg_A[7] $ D1_datab_node[7] $ F3_cout[6];

--F3_cout[7] is lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[7]
--operation mode is arithmetic

F3_cout[7] = CARRY(reg_A[7] & !D1_datab_node[7] & !F3_cout[6] # !reg_A[7] & (!F3_cout[6] # !D1_datab_node[7]));


--F3_cs_buffer[6] is lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]
--operation mode is arithmetic

F3_cs_buffer[6] = reg_A[6] $ D1_datab_node[6] $ !F3_cout[5];

--F3_cout[6] is lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6]
--operation mode is arithmetic

F3_cout[6] = CARRY(reg_A[6] & (D1_datab_node[6] # !F3_cout[5]) # !reg_A[6] & D1_datab_node[6] & !F3_cout[5]);


--F3_cs_buffer[5] is lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

F3_cs_buffer[5] = reg_A[5] $ D1_datab_node[5] $ F3_cout[4];

--F3_cout[5] is lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

F3_cout[5] = CARRY(reg_A[5] & !D1_datab_node[5] & !F3_cout[4] # !reg_A[5] & (!F3_cout[4] # !D1_datab_node[5]));


--F3_cs_buffer[4] is lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

F3_cs_buffer[4] = reg_A[4] $ D1_datab_node[4] $ !F3_cout[3];

--F3_cout[4] is lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

F3_cout[4] = CARRY(reg_A[4] & (D1_datab_node[4] # !F3_cout[3]) # !reg_A[4] & D1_datab_node[4] & !F3_cout[3]);


--F3_cs_buffer[3] is lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]
--operation mode is arithmetic

F3_cs_buffer[3] = reg_A[3] $ D1_datab_node[3] $ F3_cout[2];

--F3_cout[3] is lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

F3_cout[3] = CARRY(reg_A[3] & !D1_datab_node[3] & !F3_cout[2] # !reg_A[3] & (!F3_cout[2] # !D1_datab_node[3]));


--F3_cs_buffer[2] is lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]
--operation mode is arithmetic

F3_cs_buffer[2] = reg_A[2] $ D1_datab_node[2] $ !F3_cout[1];

--F3_cout[2] is lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

F3_cout[2] = CARRY(reg_A[2] & (D1_datab_node[2] # !F3_cout[1]) # !reg_A[2] & D1_datab_node[2] & !F3_cout[1]);


--F3_cs_buffer[1] is lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]
--operation mode is arithmetic

F3_cs_buffer[1] = reg_A[1] $ D1_datab_node[1] $ F3_cout[0];

--F3_cout[1] is lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

F3_cout[1] = CARRY(reg_A[1] & !D1_datab_node[1] & !F3_cout[0] # !reg_A[1] & (!F3_cout[0] # !D1_datab_node[1]));


--F3_cs_buffer[0] is lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]
--operation mode is arithmetic

F3_cs_buffer[0] = reg_A[0] $ reg_B[0];

--F3_cout[0] is lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic

F3_cout[0] = CARRY(reg_B[0] & reg_A[0] # !reg_B[0] & !D1_$00006);


--ex_ir[11] is ex_ir[11]
--operation mode is normal

ex_ir[11]_lut_out = id_ir[11];
ex_ir[11] = DFFE(ex_ir[11]_lut_out, clock, reset, , state);


--ex_ir[15] is ex_ir[15]
--operation mode is normal

ex_ir[15]_lut_out = id_ir[15];
ex_ir[15] = DFFE(ex_ir[15]_lut_out, clock, reset, , state);


--ex_ir[14] is ex_ir[14]
--operation mode is normal

ex_ir[14]_lut_out = id_ir[14];
e