?? mp8086.fit.talkback.xml
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<!--
This XML file (created on Fri Jan 12 16:12:47 2007) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature. To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder. For more information, go
to license.txt.
-->
<talkback>
<ver>6.0</ver>
<schema>quartus_version_6.0_build_178.xsd</schema>
<license>
<host_id>0090cccb6bda</host_id>
<nic_id>000e0c2c3096</nic_id>
<cdrive_id>b4be55b0</cdrive_id>
</license>
<tool>
<name>Quartus II</name>
<version>6.0</version>
<build>Build 178</build>
<binary_type>32</binary_type>
<module>quartus_fit</module>
<edition>Full Version</edition>
<eval>Licensed</eval>
<compilation_end_time>Fri Jan 12 16:12:47 2007</compilation_end_time>
</tool>
<machine>
<os>Windows XP</os>
<cpu>
<proc_count>2</proc_count>
<cpu_freq units="MHz">2600</cpu_freq>
</cpu>
<ram units="MB">1015</ram>
</machine>
<project>C:/work/MP8086/MP8086</project>
<revision>MP8086</revision>
<compilation_summary>
<flow_status>Successful - Fri Jan 12 16:12:47 2007</flow_status>
<quartus_ii_version>6.0 Build 178 04/27/2006 SJ Full Version</quartus_ii_version>
<revision_name>MP8086</revision_name>
<top_level_entity_name>MP8086</top_level_entity_name>
<family>APEX20KE</family>
<device>EP20K400EBC652-3</device>
<timing_models>Final</timing_models>
<met_timing_requirements>N/A</met_timing_requirements>
<total_logic_elements>5,721 / 16,640 ( 34 % )</total_logic_elements>
<total_pins>426 / 488 ( 87 % )</total_pins>
<total_virtual_pins>0</total_virtual_pins>
<total_memory_bits>4,096 / 212,992 ( 2 % )</total_memory_bits>
<total_plls>0</total_plls>
</compilation_summary>
<resource_usage_summary>
<rsc name="Registers" util="6" max=" 16640 " type="int">1040 </rsc>
<rsc name="Logic elements in carry chains" type="int">528</rsc>
<rsc name="User inserted logic elements" type="int">0</rsc>
<rsc name="Virtual pins" type="int">0</rsc>
<rsc name="I/O pins" util="87" max=" 488 " type="int">426 </rsc>
<rsc name="-- Clock pins" util="200" max=" 4 " type="int">8 </rsc>
<rsc name="-- Dedicated input pins" util="150" max=" 4 " type="int">6 </rsc>
<rsc name="Global signals" type="int">2</rsc>
<rsc name="ESBs" util="2" max=" 104 " type="int">2 </rsc>
<rsc name="Macrocells" util="0" max=" 1664 " type="int">0 </rsc>
<rsc name="ESB pterm bits used" util="0" max=" 212992 " type="int">0 </rsc>
<rsc name="ESB CAM bits used" util="0" max=" 212992 " type="int">0 </rsc>
<rsc name="Total memory bits" util="2" max=" 212992 " type="int">4096 </rsc>
<rsc name="Total RAM block bits" util="2" max=" 212992 " type="int">4096 </rsc>
<rsc name="FastRow interconnects" util="0" max=" 120 " type="int">0 </rsc>
<rsc name="LVDS transmitters" util="0" max=" 16 " type="int">0 </rsc>
<rsc name="LVDS receivers" util="0" max=" 16 " type="int">0 </rsc>
<rsc name="Maximum fan-out node" type="text">I_CLK</rsc>
<rsc name="Maximum fan-out" type="int">1056</rsc>
<rsc name="Highest non-global fan-out signal" type="text">CUEU:T_CUEU_MP8086|G_124</rsc>
<rsc name="Highest non-global fan-out" type="int">111</rsc>
<rsc name="Total fan-out" type="int">22504</rsc>
<rsc name="Average fan-out" type="float">3.65</rsc>
</resource_usage_summary>
<ram_summary>
<row>
<name>LMEM:LMEM_MP8086|lpm_ram_dpZ0:lpm_ram_dp_component|lpm_ram_dp:U1|altdpram:sram|content</name>
<mode>Dual Port</mode>
<port_a_depth>256</port_a_depth>
<port_a_width>8</port_a_width>
<port_b_depth>256</port_b_depth>
<port_b_width>8</port_b_width>
<port_a_input_registers>yes</port_a_input_registers>
<port_a_output_registers>no</port_a_output_registers>
<port_b_input_registers>yes</port_b_input_registers>
<port_b_output_registers>no</port_b_output_registers>
<size>2048</size>
<meabs>1</meabs>
<mif>C:/work/memory/L_A.mif</mif>
<location>ESB_1_D1</location>
</row>
<row>
<name>HMEM:HMEM_MP8086|LPM_RAM_DPZ0:lpm_ram_dp_component|lpm_ram_dp:U1|altdpram:sram|content</name>
<mode>Dual Port</mode>
<port_a_depth>256</port_a_depth>
<port_a_width>8</port_a_width>
<port_b_depth>256</port_b_depth>
<port_b_width>8</port_b_width>
<port_a_input_registers>yes</port_a_input_registers>
<port_a_output_registers>no</port_a_output_registers>
<port_b_input_registers>yes</port_b_input_registers>
<port_b_output_registers>no</port_b_output_registers>
<size>2048</size>
<meabs>1</meabs>
<mif>C:/work/memory/H_A.mif</mif>
<location>ESB_1_B1</location>
</row>
</ram_summary>
<mep_data>
<command_line>quartus_fit --read_settings_files=off --write_settings_files=off MP8086 -c MP8086</command_line>
</mep_data>
<software_data>
<smart_recompile>off</smart_recompile>
</software_data>
<messages>
<info>Info: Quartus II Fitter was successful. 0 errors, 0 warnings</info>
<info>Info: Elapsed time: 00:10:33</info>
<info>Info: Processing ended: Fri Jan 12 16:12:47 2007</info>
<info>Info: Fitter routing operations ending: elapsed time is 00:00:58</info>
<info>Info: Fitter routing operations beginning</info>
</messages>
<fitter_settings>
<row>
<option>Device</option>
<setting>EP20K400EBC652-3</setting>
</row>
<row>
<option>SignalProbe signals routed during normal compilation</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Use smart compilation</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Router Timing Optimization Level</option>
<setting>Normal</setting>
<default_value>Normal</default_value>
</row>
<row>
<option>Placement Effort Multiplier</option>
<setting>1.0</setting>
<default_value>1.0</default_value>
</row>
<row>
<option>Router Effort Multiplier</option>
<setting>1.0</setting>
<default_value>1.0</default_value>
</row>
<row>
<option>Optimize Timing</option>
<setting>Normal compilation</setting>
<default_value>Normal compilation</default_value>
</row>
<row>
<option>Optimize IOC Register Placement for Timing</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Limit to One Fitting Attempt</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Final Placement Optimizations</option>
<setting>Automatically</setting>
<default_value>Automatically</default_value>
</row>
<row>
<option>Fitter Aggressive Routability Optimizations</option>
<setting>Automatically</setting>
<default_value>Automatically</default_value>
</row>
<row>
<option>Fitter Initial Placement Seed</option>
<setting>1</setting>
<default_value>1</default_value>
</row>
<row>
<option>Slow Slew Rate</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>PCI I/O</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Turbo Bit</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Global Memory Control Signals</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Fitter Effort</option>
<setting>Auto Fit</setting>
<default_value>Auto Fit</default_value>
</row>
<row>
<option>Auto Global Clock</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Global Output Enable</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Global Register Control Signals</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
</fitter_settings>
<fitter_device_options>
<row>
<option>Enable user-supplied start-up clock (CLKUSR)</option>
<setting>Off</setting>
</row>
<row>
<option>Enable device-wide reset (DEV_CLRn)</option>
<setting>Off</setting>
</row>
<row>
<option>Enable device-wide output enable (DEV_OE)</option>
<setting>Off</setting>
</row>
<row>
<option>Enable INIT_DONE output</option>
<setting>Off</setting>
</row>
<row>
<option>Configuration scheme</option>
<setting>Passive Serial</setting>
</row>
<row>
<option>Reserve all unused pins</option>
<setting>As output driving ground</setting>
</row>
<row>
<option>Base pin-out file on sameframe device</option>
<setting>Off</setting>
</row>
</fitter_device_options>
<input_pins>
<row>
<name>I_CLK</name>
<pin__>T2</pin__>
<fan_out>1056</fan_out>
<global>yes</global>
<i_o_register>no</i_o_register>
<use_local_routing_input>no</use_local_routing_input>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_ce>no</single_pin_ce>
<fastrow_interconnect>no</fastrow_interconnect>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>I_RST</name>
<pin__>B19</pin__>
<fan_out>921</fan_out>
<global>yes</global>
<i_o_register>no</i_o_register>
<use_local_routing_input>no</use_local_routing_input>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_ce>no</single_pin_ce>
<fastrow_interconnect>no</fastrow_interconnect>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>I_RDY</name>
<pin__>J31</pin__>
<megalab_row>D</megalab_row>
<fan_out>4</fan_out>
<global>no</global>
<i_o_register>no</i_o_register>
<use_local_routing_input>no</use_local_routing_input>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_ce>no</single_pin_ce>
<fastrow_interconnect>no</fastrow_interconnect>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>I_S77</name>
<pin__>L1</pin__>
<megalab_row>H</megalab_row>
<fan_out>4</fan_out>
<global>no</global>
<i_o_register>no</i_o_register>
<use_local_routing_input>no</use_local_routing_input>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_ce>no</single_pin_ce>
<fastrow_interconnect>no</fastrow_interconnect>
<i_o_standard>LVTTL</i_o_standard>
</row>
</input_pins>
<output_pins>
<row>
<name>O_ALUDATA_V[0]</name>
<pin__>J5</pin__>
<megalab_row>E</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_ALUDATA_V[1]</name>
<pin__>J3</pin__>
<megalab_row>E</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_ALUDATA_V[2]</name>
<pin__>L4</pin__>
<megalab_row>G</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_ALUDATA_V[3]</name>
<pin__>M1</pin__>
<megalab_row>I</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_ALUDATA_V[4]</name>
<pin__>A16</pin__>
<megalab_col.>2</megalab_col.>
<col.>1</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_ALUDATA_V[5]</name>
<pin__>AB6</pin__>
<megalab_row>O</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_ALUDATA_V[6]</name>
<pin__>G5</pin__>
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