?? mp8086.fit.talkback.xml
字號:
<megalab_row>B</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_ALUDATA_V[7]</name>
<pin__>B14</pin__>
<megalab_col.>2</megalab_col.>
<col.>5</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_ALUDATA_V[8]</name>
<pin__>J6</pin__>
<megalab_row>E</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_ALUDATA_V[9]</name>
<pin__>A11</pin__>
<megalab_col.>2</megalab_col.>
<col.>9</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_ALUDATA_V[10]</name>
<pin__>AL13</pin__>
<megalab_col.>2</megalab_col.>
<col.>14</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_ALUDATA_V[11]</name>
<pin__>D15</pin__>
<megalab_col.>2</megalab_col.>
<col.>6</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_ALUDATA_V[12]</name>
<pin__>J4</pin__>
<megalab_row>E</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_ALUDATA_V[13]</name>
<pin__>B12</pin__>
<megalab_col.>2</megalab_col.>
<col.>10</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_ALUDATA_V[14]</name>
<pin__>AD1</pin__>
<megalab_row>R</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_ALUDATA_V[15]</name>
<pin__>A8</pin__>
<megalab_col.>2</megalab_col.>
<col.>16</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_AX_V[0]</name>
<pin__>N3</pin__>
<megalab_row>J</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_AX_V[1]</name>
<pin__>AH2</pin__>
<megalab_row>W</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_AX_V[2]</name>
<pin__>D7</pin__>
<megalab_col.>1</megalab_col.>
<col.>5</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_AX_V[3]</name>
<pin__>C6</pin__>
<megalab_col.>1</megalab_col.>
<col.>5</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_AX_V[4]</name>
<pin__>K6</pin__>
<megalab_row>F</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_AX_V[5]</name>
<pin__>K4</pin__>
<megalab_row>F</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_AX_V[6]</name>
<pin__>M6</pin__>
<megalab_row>H</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_AX_V[7]</name>
<pin__>K2</pin__>
<megalab_row>G</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_AX_V[8]</name>
<pin__>AP28</pin__>
<megalab_col.>4</megalab_col.>
<col.>14</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_AX_V[9]</name>
<pin__>AP33</pin__>
<megalab_col.>4</megalab_col.>
<col.>2</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_AX_V[10]</name>
<pin__>AP27</pin__>
<megalab_col.>4</megalab_col.>
<col.>16</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_AX_V[11]</name>
<pin__>AR30</pin__>
<megalab_col.>4</megalab_col.>
<col.>12</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_AX_V[12]</name>
<pin__>A32</pin__>
<megalab_col.>4</megalab_col.>
<col.>7</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_AX_V[13]</name>
<pin__>F33</pin__>
<megalab_row>A</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_AX_V[14]</name>
<pin__>C29</pin__>
<megalab_col.>4</megalab_col.>
<col.>8</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_AX_V[15]</name>
<pin__>E34</pin__>
<megalab_row>A</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_CX_V[0]</name>
<pin__>B30</pin__>
<megalab_col.>4</megalab_col.>
<col.>9</col.>
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