?? mp8086.fit.talkback.xml
字號:
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_BX_V[11]</name>
<pin__>G2</pin__>
<megalab_row>C</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_BX_V[12]</name>
<pin__>B20</pin__>
<megalab_col.>3</megalab_col.>
<col.>2</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_BX_V[13]</name>
<pin__>E10</pin__>
<megalab_col.>1</megalab_col.>
<col.>10</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_BX_V[14]</name>
<pin__>E15</pin__>
<megalab_col.>2</megalab_col.>
<col.>9</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_BX_V[15]</name>
<pin__>D11</pin__>
<megalab_col.>1</megalab_col.>
<col.>15</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_DX_V[0]</name>
<pin__>AE5</pin__>
<megalab_row>T</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_DX_V[1]</name>
<pin__>M35</pin__>
<megalab_row>H</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_DX_V[2]</name>
<pin__>P5</pin__>
<megalab_row>J</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_DX_V[3]</name>
<pin__>H33</pin__>
<megalab_row>C</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_DX_V[4]</name>
<pin__>C10</pin__>
<megalab_col.>1</megalab_col.>
<col.>15</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_DX_V[5]</name>
<pin__>AB5</pin__>
<megalab_row>Q</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_DX_V[6]</name>
<pin__>E9</pin__>
<megalab_col.>1</megalab_col.>
<col.>7</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>yes</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_DX_V[7]</name>
<pin__>C20</pin__>
<megalab_col.>3</megalab_col.>
<col.>2</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_DX_V[8]</name>
<pin__>AJ4</pin__>
<megalab_row>Y</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_DX_V[9]</name>
<pin__>C14</pin__>
<megalab_col.>2</megalab_col.>
<col.>8</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_DX_V[10]</name>
<pin__>E16</pin__>
<megalab_col.>2</megalab_col.>
<col.>5</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_DX_V[11]</name>
<pin__>R6</pin__>
<megalab_row>K</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_DX_V[12]</name>
<pin__>A2</pin__>
<megalab_col.>1</megalab_col.>
<col.>3</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_DX_V[13]</name>
<pin__>E14</pin__>
<megalab_col.>2</megalab_col.>
<col.>12</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_DX_V[14]</name>
<pin__>D6</pin__>
<megalab_col.>1</megalab_col.>
<col.>2</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_DX_V[15]</name>
<pin__>B8</pin__>
<megalab_col.>1</megalab_col.>
<col.>14</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_SP_V[0]</name>
<pin__>M3</pin__>
<megalab_row>I</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_SP_V[1]</name>
<pin__>T30</pin__>
<megalab_row>L</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_SP_V[2]</name>
<pin__>C5</pin__>
<megalab_col.>1</megalab_col.>
<col.>3</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_SP_V[3]</name>
<pin__>E1</pin__>
<megalab_row>C</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_SP_V[4]</name>
<pin__>C15</pin__>
<megalab_col.>2</megalab_col.>
<col.>6</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
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