?? mp8086.fit.talkback.xml
字號:
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_SP_V[5]</name>
<pin__>C1</pin__>
<megalab_row>A</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_SP_V[6]</name>
<pin__>K3</pin__>
<megalab_row>F</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_SP_V[7]</name>
<pin__>E28</pin__>
<megalab_col.>4</megalab_col.>
<col.>4</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_SP_V[8]</name>
<pin__>H31</pin__>
<megalab_row>C</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_SP_V[9]</name>
<pin__>P6</pin__>
<megalab_row>J</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_SP_V[10]</name>
<pin__>AC4</pin__>
<megalab_row>R</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_SP_V[11]</name>
<pin__>H6</pin__>
<megalab_row>C</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_SP_V[12]</name>
<pin__>D20</pin__>
<megalab_col.>3</megalab_col.>
<col.>3</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_SP_V[13]</name>
<pin__>A7</pin__>
<megalab_col.>1</megalab_col.>
<col.>14</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_SP_V[14]</name>
<pin__>D9</pin__>
<megalab_col.>1</megalab_col.>
<col.>10</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_SP_V[15]</name>
<pin__>T35</pin__>
<megalab_row>M</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_BP_V[0]</name>
<pin__>AF2</pin__>
<megalab_row>U</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_BP_V[1]</name>
<pin__>N1</pin__>
<megalab_row>J</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_BP_V[2]</name>
<pin__>D16</pin__>
<megalab_col.>2</megalab_col.>
<col.>3</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_BP_V[3]</name>
<pin__>Y5</pin__>
<megalab_row>N</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_BP_V[4]</name>
<pin__>F6</pin__>
<megalab_row>A</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_BP_V[5]</name>
<pin__>B6</pin__>
<megalab_col.>1</megalab_col.>
<col.>9</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>yes</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_BP_V[6]</name>
<pin__>AD4</pin__>
<megalab_row>S</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_BP_V[7]</name>
<pin__>B16</pin__>
<megalab_col.>2</megalab_col.>
<col.>2</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_BP_V[8]</name>
<pin__>AM16</pin__>
<megalab_col.>2</megalab_col.>
<col.>3</col.>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_BP_V[9]</name>
<pin__>K1</pin__>
<megalab_row>G</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_BP_V[10]</name>
<pin__>D10</pin__>
<megalab_col.>1</megalab_col.>
<col.>12</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_BP_V[11]</name>
<pin__>AF4</pin__>
<megalab_row>U</megalab_row>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_BP_V[12]</name>
<pin__>B26</pin__>
<megalab_col.>3</megalab_col.>
<col.>15</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_BP_V[13]</name>
<pin__>D13</pin__>
<megalab_col.>2</megalab_col.>
<col.>13</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>no</use_local_routing_output>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<single_pin_oe>no</single_pin_oe>
<single_pin_ce>no</single_pin_ce>
<open_drain>no</open_drain>
<i_o_standard>LVTTL</i_o_standard>
</row>
<row>
<name>O_BP_V[14]</name>
<pin__>C9</pin__>
<megalab_col.>1</megalab_col.>
<col.>13</col.>
<i_o_register>no</i_o_register>
<use_local_routing_output>yes</use_local_routing_output>
<power_?? 快捷鍵說明
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