-----------------------------------
--   FILE NAME : EUSR_MPX_BIU.vhd
--   FUNCTION  : select DATA (from Segment REGISTAR or from EU or IR)
--   AUTHOR    : Kazuma Mishima
--   DATE      : 10/2001
------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity EUSRMPX is
    port( I_SREGDATA :  in std_logic_vector(15 downto 0 ); --segment register data
	      I_BCUDATA  :  in std_logic_vector(15 downto 0 ); --BIU data
		  I_IRDATA   :  in std_logic_vector(15 downto 0 ); --IR data
		  I_EUCDATA  :  in std_logic_vector(15 downto 0 ); --EUC data
		  I_2EU      :  in std_logic; --Set EUC data signal 
		  I_RDIR     :  in std_logic; --read IR signal
          I_RDSR     :  in std_logic; --segment register read signal
          O_BIUDATA  : out std_logic_vector(15 downto 0 ) --out data to EU
		  ); 
end EUSRMPX;

architecture RTL of EUSRMPX is

begin
	process(I_RDSR,I_RDIR,I_SREGDATA,I_BCUDATA,I_IRDATA,I_EUCDATA,I_2EU)
	begin
		if    ((I_RDSR='1' and I_RDIR='0') and I_2EU ='0')then --read segment register
			O_BIUDATA <= I_SREGDATA;							
		elsif ((I_RDSR='0' and I_RDIR='1') and I_2EU ='0')then --read IR
			O_BIUDATA <= I_IRDATA;							
		elsif ((I_RDSR='0' and I_RDIR='0') and I_2EU ='1')then --EUC data out
			O_BIUDATA <= I_EUCDATA;
  		else
			O_BIUDATA <= I_BCUDATA;
		end if;
	 end process;

end RTL;