library ieee;
use ieee.STD_LOGIC_1164.all;
library synplify;
use synplify.attributes.all;
 
entity EACU is
	port( I_CLK         :  in std_logic;
          I_RST         :  in std_logic;
          I_MOD         :  in std_logic_vector( 1 downto 0 );
          I_RM          :  in std_logic_vector( 2 downto 0 );
          I_BW          :  in std_logic;
          I_EA          :  in std_logic;
          I_QUEEMPTY    :  in std_logic;
          O_BUSCS       : out std_logic_vector( 4 downto 0 );
          O_D16HL       : out std_logic;
          O_EARQ        : out std_logic;
          O_GRSEL       : out std_logic_vector( 3 downto 0 );
          O_RDQUE       : out std_logic;
          O_SE          : out std_logic;
          O_EACUSTATE_V : out std_logic_vector( 2 downto 0 );
          O_TMPRW       : out std_logic_vector( 1 downto 0 )
          ); 
end EACU;
 
architecture RTL of EACU is
 
signal EAFSM_EACUSTATE : std_logic_vector( 2 downto 0 );

component STDEC
	port( I_MOD			:  in std_logic_vector( 1 downto 0 );	--mod in op code 
		  I_RM	        :  in std_logic_vector( 2 downto 0 );	--rm in op code
		  I_BW			:  in std_logic; --byte or word
		  I_EACUSTATE	:  in std_logic_vector( 2 downto 0 );	--EA state
	      O_EACUSTATE_V : out std_logic_vector( 2 downto 0 ); --for test
		  O_EARQ	    : out std_logic; --mem(EA)value request 
		  O_RDQUE	    : out std_logic; --read que signal
		  O_SE          : out std_logic; --disp sign extension(<='1') 
		  O_TMPRW	    : out std_logic_vector( 1 downto 0 );	--TMPreg read or write(00:read,01:tmp1 write,10:tmp2 write,11:write)
		  O_D16HL	    : out std_logic; --displacement-high or low
		  O_BUSCS	    : out std_logic_vector( 4 downto 0 );	--bus cotrol
		  O_GRSEL	    : out std_logic_vector( 3 downto 0 )  --GR select
		  ); 
end component;

component EAFSM
	port( I_CLK       :  in std_logic;
          I_RST       :  in std_logic;
          I_QUEEMPTY  :  in std_logic;
          I_BW        :  in std_logic;
          I_EA        :  in std_logic;
          I_RM        :  in std_logic_vector( 2 downto 0 );
          I_MOD       :  in std_logic_vector( 1 downto 0 );
          O_EACUSTATE : out std_logic_vector( 2 downto 0 )
          );
end component; 

begin
 
	STDEC_EACU : STDEC
	port map( 
		I_MOD => I_MOD,
		I_RM => I_RM,
		I_BW => I_BW,
		I_EACUSTATE => EAFSM_EACUSTATE,
	    O_EACUSTATE_V => O_EACUSTATE_V,
		O_EARQ => O_EARQ,
		O_RDQUE => O_RDQUE,
		O_SE => O_SE,
		O_TMPRW => O_TMPRW,
		O_D16HL => O_D16HL,
		O_BUSCS => O_BUSCS,
		O_GRSEL => O_GRSEL
		); 
 
	EAFSM_EACU : EAFSM
	port map( 
		I_CLK => I_CLK,
        I_RST => I_RST,
        I_QUEEMPTY => I_QUEEMPTY,
        I_BW => I_BW,
        I_EA => I_EA,
        I_RM => I_RM,
        I_MOD => I_MOD,
        O_EACUSTATE => EAFSM_EACUSTATE
        );

end RTL;