-----------------------------------
--   FILE NAME : adder_ADD.vhd
--   FUNCTION  : Create 20bit adress(Asynchronous)
--   AUTHOR    : Kazuma Mishima
--   DATE      : 5/2001
------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ADDADR is
	generic( SRW   : integer :=16;
	         IRW   : integer :=16;
			 PADRW : integer :=20
			 );
    port( I_SREGDATA :  in std_logic_vector(SRW-1 downto 0); --input segment data
          I_IPIRDATA :  in std_logic_vector(IRW-1 downto 0); --input IP or IR 
		  I_EAPLUS2  :  in std_logic ; -- '1' => EA+2	
		  O_PADR     : out std_logic_vector(PADRW-1 downto 0)  --OUT Adress(20bit)
		   );                    		  
end ADDADR;

architecture RTL of ADDADR is
begin         
--addition
	process(I_SREGDATA,I_IPIRDATA,I_EAPLUS2)
	begin
    	if(I_EAPLUS2 = '1')then
			O_PADR <= ((I_SREGDATA&"0000")+("0000"&I_IPIRDATA))+"00000000000000000010";  --EA +2
		else
    	    O_PADR <=  (I_SREGDATA&"0000")+("0000"&I_IPIRDATA);
		end if;
    end process;
  
end RTL;