library ieee;
use ieee.STD_LOGIC_1164.all;
library synplify;
use synplify.attributes.all;
  
entity CU is
	port( I_CLK         :  in std_logic;
          I_RST         :  in std_logic;
          I_MOD         :  in std_logic_vector( 1 downto 0 );
          I_RM          :  in std_logic_vector( 2 downto 0 );
		  I_BW          :  in std_logic;
          I_EA          :  in std_logic;
          I_RDQUE       :  in std_logic;
          I_D16HL       :  in std_logic;
          I_SE          :  in std_logic;
          I_TMPRW       :  in std_logic_vector( 1 downto 0 );
          I_BUSCS       :  in std_logic_vector( 4 downto 0 );
          I_GRSEL       :  in std_logic_vector( 3 downto 0 );
          I_QUEEMPTY    :  in std_logic;
          I_BDATA       :  in std_logic_vector( 7 downto 0 );
          I_BIUDATA     :  in std_logic_vector(15 downto 0 );
          O_D16HL       : out std_logic;
          O_RDQUE       : out std_logic;
          O_SE          : out std_logic;
          O_BUSCS       : out std_logic_vector( 4 downto 0 );
          O_GRSEL       : out std_logic_vector( 3 downto 0 );
          O_TMPRW       : out std_logic_vector( 1 downto 0 );
          O_BIUDATA     : out std_logic_vector(15 downto 0 );
          O_EARQ        : out std_logic;
          O_EACUSTATE_V : out std_logic_vector( 2 downto 0 )
		  ); 
end CU;
  
use work.all;
architecture RTL of CU is
 
signal STDEC_BUSCS : std_logic_vector( 4 downto 0 );
signal STDEC_D16HL : std_logic;
signal STDEC_GRSEL : std_logic_vector( 3 downto 0 );
signal STDEC_RDQUE : std_logic;
signal STDEC_SE    : std_logic;
signal STDEC_TMPRW : std_logic_vector( 1 downto 0 );

component EACU
	port( I_CLK         :  in std_logic;
          I_RST         :  in std_logic;
          I_MOD         :  in std_logic_vector( 1 downto 0 );
          I_RM          :  in std_logic_vector( 2 downto 0 );
          I_BW          :  in std_logic;
          I_EA          :  in std_logic;
          I_QUEEMPTY    :  in std_logic;
          O_BUSCS       : out std_logic_vector( 4 downto 0 );
          O_D16HL       : out std_logic;
          O_EARQ        : out std_logic;
          O_GRSEL       : out std_logic_vector( 3 downto 0 );
          O_RDQUE       : out std_logic;
          O_SE          : out std_logic;
          O_EACUSTATE_V : out std_logic_vector( 2 downto 0 );
          O_TMPRW       : out std_logic_vector( 1 downto 0 )
          ); 
end component;

component MPX12IN6OUT
	generic( --S1W : integer :=  1; 
			 --S2W : integer :=  1;
			 --S3W : integer :=  1;
			 S4W : integer :=  2;
			 S5W : integer :=  4;
			 S6W : integer :=  5
			 );
	port( I_SW     :  in std_logic;
		  I_DATA11 :  in std_logic;           
		  I_DATA12 :  in std_logic;
          I_DATA13 :  in std_logic;
          I_DATA14 :  in std_logic_vector(S4W-1 downto 0 );
		  I_DATA15 :  in std_logic_vector(S5W-1 downto 0 );
		  I_DATA16 :  in std_logic_vector(S6W-1 downto 0 );
          I_DATA01 :  in std_logic;
          I_DATA02 :  in std_logic;
          I_DATA03 :  in std_logic;
          I_DATA04 :  in std_logic_vector(S4W-1 downto 0 );
		  I_DATA05 :  in std_logic_vector(S5W-1 downto 0 );
		  I_DATA06 :  in std_logic_vector(S6W-1 downto 0 );
          O_DATA1  : out std_logic;
          O_DATA2  : out std_logic;
          O_DATA3  : out std_logic;
	   	  O_DATA4  : out std_logic_vector(S4W-1 downto 0);
	      O_DATA5  : out std_logic_vector(S5W-1 downto 0);
          O_DATA6  : out std_logic_vector(S6W-1 downto 0)
		  );
end component;

component MPX2IN1OUTA
	generic( IDW0 : integer ;
			 IDW1 : integer ; --memory WORD
			 ODW  : integer 
			 ); 
	port( I_SW     :  in std_logic;    
		  I_DATA01 :  in std_logic_vector( IDW0-1 downto 0 ); --I_EN=0
          I_DATA11 :  in std_logic_vector( IDW1-1 downto 0 ); --I_EN=1
          O_DATA   : out std_logic_vector( ODW-1  downto 0 )
		  );  
end component; 

begin
 
	T_EACU_CU : EACU
	port map( 
		I_CLK => I_CLK,
        I_RST => I_RST,
        I_MOD => I_MOD,
        I_RM => I_RM,
        I_BW => I_BW,
        I_EA => I_EA,
        I_QUEEMPTY => I_QUEEMPTY,
        O_BUSCS => STDEC_BUSCS,
        O_D16HL => STDEC_D16HL,
        O_EARQ => O_EARQ,
        O_GRSEL => STDEC_GRSEL,
        O_RDQUE => STDEC_RDQUE,
        O_SE => STDEC_SE,
        O_EACUSTATE_V => O_EACUSTATE_V,
        O_TMPRW => STDEC_TMPRW
        ); 

	MPX12IN6OUT_CU : MPX12IN6OUT
	generic map( 
		S4W => 2,
		S5W => 4,
		S6W => 5
		)
    port map( 
        I_SW => I_EA,
        I_DATA11 => STDEC_RDQUE,
		I_DATA12 => STDEC_D16HL,
		I_DATA13 => STDEC_SE,
        I_DATA14 => STDEC_TMPRW,
		I_DATA15 => STDEC_GRSEL,
		I_DATA16 => STDEC_BUSCS,
        I_DATA01 => I_RDQUE,
		I_DATA02 => I_D16HL,
		I_DATA03 => I_SE,
        I_DATA04 => I_TMPRW,
        I_DATA05 => I_GRSEL,
        I_DATA06 => I_BUSCS,
        O_DATA1 => O_RDQUE,
	   	O_DATA2 => O_D16HL,
	    O_DATA3 => O_SE,
        O_DATA4 => O_TMPRW,
        O_DATA5 => O_GRSEL,
        O_DATA6 => O_BUSCS
		);
 
	MPX2IN1OUTA_CU : MPX2IN1OUTA
	generic map( 
		IDW0 => 16,
		IDW1 => 8,
		ODW => 16
		)
	port map( 
        I_SW => I_EA,
		I_DATA01 => I_BIUDATA,
        I_DATA11 => I_BDATA,
        O_DATA => O_BIUDATA
		);  

end RTL;