{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 25 10:17:01 2008 " "Info: Processing started: Sun May 25 10:17:01 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off PLL2 -c PLL2 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off PLL2 -c PLL2" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "PLL2 EP1S10B672C6 " "Info: Selected device EP1S10B672C6 for design \"PLL2\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "ICUT_CUT_YGR_PLL_DETERMINED_TYPE" "Enhanced altpll:altpll_component\|pll " "Info: Implemented Enhanced for PLL \"altpll:altpll_component\|pll\"" {  } {  } 0 0 "Implemented %1!s! for PLL \"%2!s!\"" 0 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL \"altpll:altpll_component\|pll\"" { { "Info" "ICUT_PLL_PRESERVE_COUNTER_ORDER_OPTION_USED" "real-time reconfiguration is being used " "Info: Clock router will preserve the counter order because real-time reconfiguration is being used" {  } {  } 0 0 "Clock router will preserve the counter order because %1!s!" 0 0} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "altpll:altpll_component\|_clk0 1 1 0 0 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll:altpll_component\|_clk0 port" {  } {  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "altpll:altpll_component\|_clk1 1 1 180 50000 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 180 degrees (50000 ps) for altpll:altpll_component\|_clk1 port" {  } {  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "altpll:altpll_component\|_clk2 1 1 0 0 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll:altpll_component\|_clk2 port" {  } {  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "altpll:altpll_component\|_extclk0 2 1 0 0 " "Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll:altpll_component\|_extclk0 port" {  } {  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "altpll:altpll_component\|_extclk1 1 2 0 0 " "Info: Implementing clock multiplication of 1, clock division of 2, and phase shift of 0 degrees (0 ps) for altpll:altpll_component\|_extclk1 port" {  } {  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0}  } { { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 111 -1 0 } }  } 0 0 "Implementing parameter values for PLL \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S20B672C6 " "Info: Device EP1S20B672C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S25B672C6 " "Info: Device EP1S25B672C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFIOMGR_PINS_MISSING_LOCATION_INFO" "12 12 " "Info: No exact pin location assignment(s) for 12 pins of 12 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "c0 " "Info: Pin c0 not assigned to an exact location on the device" {  } { { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 55 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "c0" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { c0 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { c0 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "c1 " "Info: Pin c1 not assigned to an exact location on the device" {  } { { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 56 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "c1" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { c1 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { c1 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "c2 " "Info: Pin c2 not assigned to an exact location on the device" {  } { { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 57 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "c2" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { c2 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { c2 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "e0 " "Info: Pin e0 not assigned to an exact location on the device" {  } { { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 58 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "e0" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { e0 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { e0 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "e1 " "Info: Pin e1 not assigned to an exact location on the device" {  } { { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 59 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "e1" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { e1 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { e1 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "locked " "Info: Pin locked not assigned to an exact location on the device" {  } { { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 60 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "locked" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { locked } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { locked } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "scandataout " "Info: Pin scandataout not assigned to an exact location on the device" {  } { { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 61 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "scandataout" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { scandataout } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { scandataout } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "areset " "Info: Pin areset not assigned to an exact location on the device" {  } { { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 50 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "areset" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { areset } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { areset } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "scanclk " "Info: Pin scanclk not assigned to an exact location on the device" {  } { { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 53 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "scanclk" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { scanclk } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { scanclk } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "scanaclr " "Info: Pin scanaclr not assigned to an exact location on the device" {  } { { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 52 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "scanaclr" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { scanaclr } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { scanaclr } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "scandata " "Info: Pin scandata not assigned to an exact location on the device" {  } { { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 54 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "scandata" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { scandata } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { scandata } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "inclk0 " "Info: Pin inclk0 not assigned to an exact location on the device" {  } { { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 51 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "inclk0" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { inclk0 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { inclk0 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "altpll:altpll_component\|_clk0 " "Info: Promoted signal \"altpll:altpll_component\|_clk0\" to use global clock" {  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "altpll:altpll_component\|_clk0" } { 0 "altpll:altpll_component\|_clk0" } } } } { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 111 -1 0 } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altpll:altpll_component|_clk0 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock" 0 0} { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "altpll:altpll_component\|_clk1 " "Info: Promoted signal \"altpll:altpll_component\|_clk1\" to use global clock" {  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "altpll:altpll_component\|_clk1" } { 0 "altpll:altpll_component\|_clk0" } } } } { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 111 -1 0 } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altpll:altpll_component|_clk0 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock" 0 0} { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "altpll:altpll_component\|_clk2 " "Info: Promoted signal \"altpll:altpll_component\|_clk2\" to use global clock" {  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "altpll:altpll_component\|_clk2" } { 0 "altpll:altpll_component\|_clk0" } } } } { "PLL2.v" "" { Text "C:/altera/work/PLL/PLL2/PLL2/PLL2.v" 111 -1 0 } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altpll:altpll_component|_clk0 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock" 0 0}  } {  } 0 0 "Promoted PLL clock signals" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}