`timescale 1ns / 100psmodule top(                         // input port                                                                        clk_in, // 1s               rst_n,                   // out port              lcd_e,                   lcd_rs,                  lcd_rw,                  lcd_data      );   // input signal                input              clk_in;        input              rst_n;      // output signal               output             lcd_e;      output             lcd_rs;     output             lcd_rw;     output [7:0]       lcd_data;   //             wire             clk_in;                     wire             rst_n;                    wire             lcd_e;      wire             lcd_rs;     wire             lcd_rw;     wire [7:0]       lcd_data;   //wire             clk_out; //--------------------------------------           clk_div U_div(                                  //input port                      .clk_in(clk_in), // 50Mhz                  .rst_n(rst_n),                            //output port                     .clk_out(clk_out) // 1s       );                                 lcd_control U_lcd(                                                   // input port                   .clk(clk_out), // 1s                      //.clk(clk_in), // 50Mhz                  .rst_n(rst_n),                          // out port                     .lcd_e(lcd_e),                          .lcd_rs(lcd_rs),                         .lcd_rw(lcd_rw),                         .lcd_data(lcd_data)      );                              endmodule