library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity tralc is
    Port ( clk : in std_logic;
           s : in std_logic;
           rst : in std_logic;
           MG : out std_logic;
           MY : out std_logic;
           MR : out std_logic;
           CG : out std_logic;
           CY : out std_logic;
           CR : out std_logic);
end tralc;

architecture Behavioral of tralc is
   constant timemax: integer :=60;--3600;
	constant timeMGCR: integer :=60;
	constant timeMYCR: integer :=4;
	constant timeMRCG: integer :=20;
	constant timeMRCY: integer :=4;
	type state is (MGCR, stby, MYCR, MRCG, MRCY);
	signal pr_state, nx_state: state;
	signal time: integer range 0 to timemax;
begin
------------lower section of state machine-------
	process (clk,rst)
	variable count: integer range 0 to timemax;
	begin
	if(rst = '1') then pr_state<=MGCR;
	count :=0;
	elsif (clk'event and clk = '1') then
	count := count+1;
              if (count>=time) then
	pr_state <= nx_state;
	count := 0;
	end if;
	end if;
	end process;
	----------upper section of state machine:--------
	process (pr_state,s)
	begin
	case pr_state is
	 when	MGCR =>
	     MG <= '1'; MY <= '0'; MR <= '0'; CG <= '0'; CY <= '0'; CR <= '1';
		 nx_state <= stby;
			   time <= timeMGCR;
	 when stby =>
	     MG <= '1'; MY <= '0'; MR <= '0'; CG <= '0'; CY <= '0'; CR <= '1';
		if (s='0') then  nx_state <= stby;
			elsif (s='1') then nx_state <=MYCR;
		end if;
		time <= 0;
	 when	MYCR =>
	     MG <= '0'; MY <= '1'; MR <= '0'; CG <= '0'; CY <= '0'; CR <= '1';
		nx_state <=MRCG;
		time <= timeMYCR;
			 
	 when	MRCG=>
	     MG <= '0'; MY <= '0'; MR <= '1'; CG <= '1'; CY <= '0'; CR <= '0';			                             if (s='1') then time <=timeMRCG  ;nx_state <= MRCY;
                                          elsif (s='0') then  time <=0 ;nx_state <= MRCY;
                             end if;
	 when	MRCY =>
	     MG <= '0'; MY <= '0'; MR <= '1'; CG <= '0'; CY <= '1'; CR <= '0';
		 nx_state <=MGCR;
			time <=timeMRCY;			
	end case;
  end process;
end Behavioral;