?? controller.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
entity controller IS
PORT
(clock,hold:in std_logic;
countnum:in integer range 0 to 49;
numa,numb:out integer range 0 to 25;
reda,greena,yellowa:out std_logic;
redb,greenb,yellowb:out std_logic;
flash:out std_logic);
end;
architecture behavior of controller is
begin
process(clock)
begin
if falling_edge(clock) then
if hold='1' then
reda<='1';
redb<='1';
greena<='0';
greenb<='0';
yellowa<='0';
yellowb<='0';
flash<='1';
else
flash<='0';
if countnum<=19 then
numa<=20-countnum;
reda<='0';
greena<='1';
yellowa<='0';
elsif countnum<=24 then
numa<=25-countnum;
reda<='0';
greena<='0';
yellowa<='1';
else
numa<=50-countnum;
reda<='1';
greena<='0';
yellowa<='0';
end if;
if countnum<=24 then
numa<=25-countnum;
reda<='1';
greena<='0';
yellowa<='0';
elsif countnum<=44 then
numa<=45-countnum;
reda<='0';
greena<='1';
yellowa<='0';
else
numa<=50-countnum;
reda<='0';
greena<='0';
yellowa<='1';
end if;
end if;
end if;
end process;
end;
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