?? taxi.tan.qmsg
字號:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "taxi.vhd" "" { Text "D:/pro1/taxi.vhd" 9 -1 0 } } { "c:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register mm\[0\] register mm\[10\] 38.31 MHz 26.1 ns Internal " "Info: Clock \"clk\" has Internal fmax of 38.31 MHz between source register \"mm\[0\]\" and destination register \"mm\[10\]\" (period= 26.1 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "22.500 ns + Longest register register " "Info: + Longest register to register delay is 22.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mm\[0\] 1 REG LC3_C17 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_C17; Fanout = 5; REG Node = 'mm\[0\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { mm[0] } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/pro1/taxi.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(1.200 ns) 3.500 ns lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\] 2 COMB LC3_C13 1 " "Info: 2: + IC(2.300 ns) + CELL(1.200 ns) = 3.500 ns; Loc. = LC3_C13; Fanout = 1; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { mm[0] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 3.800 ns lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 3 COMB LC4_C13 1 " "Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 3.800 ns; Loc. = LC4_C13; Fanout = 1; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.300 ns" { lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.100 ns lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 4 COMB LC5_C13 1 " "Info: 4: + IC(0.000 ns) + CELL(0.300 ns) = 4.100 ns; Loc. = LC5_C13; Fanout = 1; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.300 ns" { lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.400 ns lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 5 COMB LC6_C13 2 " "Info: 5: + IC(0.000 ns) + CELL(0.300 ns) = 4.400 ns; Loc. = LC6_C13; Fanout = 2; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.300 ns" { lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.700 ns lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 6 COMB LC7_C13 2 " "Info: 6: + IC(0.000 ns) + CELL(0.300 ns) = 4.700 ns; Loc. = LC7_C13; Fanout = 2; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.300 ns" { lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 5.000 ns lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 7 COMB LC8_C13 2 " "Info: 7: + IC(0.000 ns) + CELL(0.300 ns) = 5.000 ns; Loc. = LC8_C13; Fanout = 2; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.300 ns" { lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.300 ns) 6.100 ns lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\] 8 COMB LC1_C15 2 " "Info: 8: + IC(0.800 ns) + CELL(0.300 ns) = 6.100 ns; Loc. = LC1_C15; Fanout = 2; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.100 ns" { lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 7.400 ns lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[7\] 9 COMB LC2_C15 2 " "Info: 9: + IC(0.000 ns) + CELL(1.300 ns) = 7.400 ns; Loc. = LC2_C15; Fanout = 2; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[7\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.800 ns) 11.400 ns mm~948 10 COMB LC2_C16 2 " "Info: 10: + IC(2.200 ns) + CELL(1.800 ns) = 11.400 ns; Loc. = LC2_C16; Fanout = 2; COMB Node = 'mm~948'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] mm~948 } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/pro1/taxi.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 14.300 ns Equal1~55 11 COMB LC1_C16 1 " "Info: 11: + IC(0.600 ns) + CELL(2.300 ns) = 14.300 ns; Loc. = LC1_C16; Fanout = 1; COMB Node = 'Equal1~55'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { mm~948 Equal1~55 } "NODE_NAME" } } { "c:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 18.800 ns Equal1~56 12 COMB LC2_C18 6 " "Info: 12: + IC(2.200 ns) + CELL(2.300 ns) = 18.800 ns; Loc. = LC2_C18; Fanout = 6; COMB Node = 'Equal1~56'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { Equal1~55 Equal1~56 } "NODE_NAME" } } { "c:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.200 ns) 22.500 ns mm\[10\] 13 REG LC3_C23 6 " "Info: 13: + IC(2.500 ns) + CELL(1.200 ns) = 22.500 ns; Loc. = LC3_C23; Fanout = 6; REG Node = 'mm\[10\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { Equal1~56 mm[10] } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/pro1/taxi.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.900 ns ( 52.89 % ) " "Info: Total cell delay = 11.900 ns ( 52.89 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.600 ns ( 47.11 % ) " "Info: Total interconnect delay = 10.600 ns ( 47.11 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "22.500 ns" { mm[0] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] mm~948 Equal1~55 Equal1~56 mm[10] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "22.500 ns" { mm[0] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] mm~948 Equal1~55 Equal1~56 mm[10] } { 0.000ns 2.300ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.800ns 0.000ns 2.200ns 0.600ns 2.200ns 2.500ns } { 0.000ns 1.200ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 1.300ns 1.800ns 2.300ns 2.300ns 1.200ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 12 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 12; CLK Node = 'clk'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/pro1/taxi.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns mm\[10\] 2 REG LC3_C23 6 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC3_C23; Fanout = 6; REG Node = 'mm\[10\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { clk mm[10] } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/pro1/taxi.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk mm[10] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out mm[10] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 12 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 12; CLK Node = 'clk'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/pro1/taxi.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns mm\[0\] 2 REG LC3_C17 5 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC3_C17; Fanout = 5; REG Node = 'mm\[0\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { clk mm[0] } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/pro1/taxi.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk mm[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out mm[0] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk mm[10] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out mm[10] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk mm[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out mm[0] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" { } { { "taxi.vhd" "" { Text "D:/pro1/taxi.vhd" 22 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" { } { { "taxi.vhd" "" { Text "D:/pro1/taxi.vhd" 22 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "22.500 ns" { mm[0] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] mm~948 Equal1~55 Equal1~56 mm[10] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "22.500 ns" { mm[0] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] mm~948 Equal1~55 Equal1~56 mm[10] } { 0.000ns 2.300ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.800ns 0.000ns 2.200ns 0.600ns 2.200ns 2.500ns } { 0.000ns 1.200ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 1.300ns 1.800ns 2.300ns 2.300ns 1.200ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk mm[10] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out mm[10] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk mm[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out mm[0] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk en1 mm\[7\] 18.400 ns register " "Info: tco from clock \"clk\" to destination pin \"en1\" through register \"mm\[7\]\" is 18.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.300 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 12 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 12; CLK Node = 'clk'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/pro1/taxi.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns mm\[7\] 2 REG LC4_C16 6 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_C16; Fanout = 6; REG Node = 'mm\[7\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { clk mm[7] } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/pro1/taxi.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk mm[7] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out mm[7] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" { } { { "taxi.vhd" "" { Text "D:/pro1/taxi.vhd" 22 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.000 ns + Longest register pin " "Info: + Longest register to pin delay is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mm\[7\] 1 REG LC4_C16 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_C16; Fanout = 6; REG Node = 'mm\[7\]'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { mm[7] } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/pro1/taxi.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(1.700 ns) 4.300 ns LessThan0~78 2 COMB LC1_C23 1 " "Info: 2: + IC(2.600 ns) + CELL(1.700 ns) = 4.300 ns; Loc. = LC1_C23; Fanout = 1; COMB Node = 'LessThan0~78'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.300 ns" { mm[7] LessThan0~78 } "NODE_NAME" } } { "c:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 5.800 ns LessThan0~75 3 COMB LC2_C23 1 " "Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 5.800 ns; Loc. = LC2_C23; Fanout = 1; COMB Node = 'LessThan0~75'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { LessThan0~78 LessThan0~75 } "NODE_NAME" } } { "c:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(5.100 ns) 12.000 ns en1 4 PIN PIN_78 0 " "Info: 4: + IC(1.100 ns) + CELL(5.100 ns) = 12.000 ns; Loc. = PIN_78; Fanout = 0; PIN Node = 'en1'" { } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.200 ns" { LessThan0~75 en1 } "NODE_NAME" } } { "taxi.vhd" "" { Text "D:/pro1/taxi.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.300 ns ( 69.17 % ) " "Info: Total cell delay = 8.300 ns ( 69.17 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.700 ns ( 30.83 % ) " "Info: Total interconnect delay = 3.700 ns ( 30.83 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { mm[7] LessThan0~78 LessThan0~75 en1 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { mm[7] LessThan0~78 LessThan0~75 en1 } { 0.000ns 2.600ns 0.000ns 1.100ns } { 0.000ns 1.700ns 1.500ns 5.100ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk mm[7] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out mm[7] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { mm[7] LessThan0~78 LessThan0~75 en1 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { mm[7] LessThan0~78 LessThan0~75 en1 } { 0.000ns 2.600ns 0.000ns 1.100ns } { 0.000ns 1.700ns 1.500ns 5.100ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "98 " "Info: Allocated 98 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu May 31 11:58:48 2007 " "Info: Processing ended: Thu May 31 11:58:48 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
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