`timescale 1ns / 10ps
module test;
	reg sys_clk;
	reg sys_rst;
	reg [3:0]sys_s;
	reg [7:0]sys_in;
	
	wire [7:0]out;
	
	shift st(sys_clk,sys_rst,sys_s,sys_in,out);

	initial
		begin
			$dumpfile("test_out.fsdb");
			$dumpvars;
		end
	
	initial begin
		// Initialize Inputs
		sys_rst = 1;
		sys_clk = 0;
		sys_in = 8'hx;
		sys_s = 4'hx;
		#40;
		sys_rst = 0;		
		// Wait 100 ns for global reset to finish
		#100;
		sys_rst = 1;    
		#20;	
    sys_s = 4'h8;
    #30;
    sys_in = 8'b0010_0101;
    #40
    sys_s = 4'h1;
    #60
    sys_s = 4'h0;
    #20
    sys_in = 8'b0001_0000;
    #15
    sys_s = 4'h2;
    #40
    sys_s = 4'he;
    #40
    sys_s = 4'h3;
    #40
    sys_s = 4'hd;
    #40
    sys_s = 4'h4;
    #40
    sys_s = 4'hc;
    #60
    sys_rst = 0;
    #60
    sys_rst = 1;
    #40
    sys_s = 4'h5;
    #40
    sys_s = 4'hb;
    #40
    sys_s = 4'h6;
    #40
    sys_s = 4'ha;
    #40
    sys_s = 4'h7;
    #40
    sys_s = 4'h9;
    #40
    sys_s = 4'h8;

    
		// Add stimulus here

	end
  always #20 sys_clk=~sys_clk;   
  
  initial
  #1000 $finish;
endmodule