?? ram_cpremove.vhd
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-- megafunction wizard: %RAM: 2-PORT%CBX%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_CPRemove.vhd
-- Megafunction Name(s):
-- altsyncram
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altsyncram ADDRESS_ACLR_A="CLEAR0" ADDRESS_ACLR_B="CLEAR0" ADDRESS_REG_B="CLOCK0" DEVICE_FAMILY="Cyclone" INDATA_ACLR_A="CLEAR0" NUMWORDS_A=80 NUMWORDS_B=80 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="CLEAR0" OUTDATA_REG_B="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" RDCONTROL_ACLR_B="CLEAR0" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=10 WIDTH_B=10 WIDTH_BYTEENA_A=1 WIDTHAD_A=7 WIDTHAD_B=7 WRCONTROL_ACLR_A="CLEAR0" aclr0 address_a address_b clock0 data_a q_b rden_b wren_a
--VERSION_BEGIN 5.1 cbx_altsyncram 2005:11:08:14:10:50:SJ cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_lpm_add_sub 2005:11:02:10:42:42:SJ cbx_lpm_compare 2005:07:11:09:41:28:SJ cbx_lpm_decode 2005:04:27:14:28:48:SJ cbx_lpm_mux 2005:12:13:16:24:06:SJ cbx_mgl 2006:01:12:16:15:18:SJ cbx_stratix 2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ cbx_util_mgl 2005:09:12:10:23:22:SJ VERSION_END
LIBRARY cyclone;
USE cyclone.all;
--synthesis_resources = M4K 10
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ram_CPRemove_altsyncram_57e1 IS
PORT
(
aclr0 : IN STD_LOGIC := '0';
address_a : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (6 DOWNTO 0) := (OTHERS => '1');
clock0 : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0) := (OTHERS => '1');
q_b : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
rden_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0'
);
END ram_CPRemove_altsyncram_57e1;
ARCHITECTURE RTL OF ram_CPRemove_altsyncram_57e1 IS
ATTRIBUTE synthesis_clearbox : boolean;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
ATTRIBUTE ALTERA_ATTRIBUTE : string;
ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SIGNAL wire_ram_block1a_0portaaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block1a_1portaaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block1a_2portaaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block1a_3portaaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block1a_4portaaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block1a_5portaaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block1a_6portaaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block1a_7portaaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block1a_8portaaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block1a_9portaaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block1a_0portadatain : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block1a_1portadatain : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block1a_2portadatain : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block1a_3portadatain : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block1a_4portadatain : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block1a_5portadatain : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block1a_6portadatain : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block1a_7portadatain : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block1a_8portadatain : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block1a_9portadatain : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block1a_portawe : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_ram_block1a_0portbaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block1a_1portbaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block1a_2portbaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block1a_3portbaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block1a_4portbaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block1a_5portbaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block1a_6portbaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block1a_7portbaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block1a_8portbaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block1a_9portbaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block1a_0portbdataout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block1a_1portbdataout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block1a_2portbdataout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block1a_3portbdataout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block1a_4portbdataout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block1a_5portbdataout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block1a_6portbdataout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block1a_7portbdataout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block1a_8portbdataout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block1a_9portbdataout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL address_a_wire : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL address_b_wire : STD_LOGIC_VECTOR (6 DOWNTO 0);
COMPONENT cyclone_ram_block
GENERIC
(
CONNECTIVITY_CHECKING : STRING := "OFF";
DATA_INTERLEAVE_OFFSET_IN_BITS : NATURAL := 1;
DATA_INTERLEAVE_WIDTH_IN_BITS : NATURAL := 1;
INIT_FILE : STRING := "UNUSED";
INIT_FILE_LAYOUT : STRING := "UNUSED";
LOGICAL_RAM_NAME : STRING;
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
MIXED_PORT_FEED_THROUGH_MODE : STRING := "UNUSED";
OPERATION_MODE : STRING;
PORT_A_ADDRESS_CLEAR : STRING := "UNUSED";
PORT_A_ADDRESS_WIDTH : NATURAL := 1;
PORT_A_BYTE_ENABLE_CLEAR : STRING := "UNUSED";
PORT_A_BYTE_ENABLE_MASK_WIDTH : NATURAL := 1;
PORT_A_DATA_IN_CLEAR : STRING := "UNUSED";
PORT_A_DATA_OUT_CLEAR : STRING := "UNUSED";
PORT_A_DATA_OUT_CLOCK : STRING := "none";
PORT_A_DATA_WIDTH : NATURAL := 1;
PORT_A_FIRST_ADDRESS : NATURAL;
PORT_A_FIRST_BIT_NUMBER : NATURAL;
PORT_A_LAST_ADDRESS : NATURAL;
PORT_A_LOGICAL_RAM_DEPTH : NATURAL := 0;
PORT_A_LOGICAL_RAM_WIDTH : NATURAL := 0;
PORT_A_WRITE_ENABLE_CLEAR : STRING := "UNUSED";
PORT_B_ADDRESS_CLEAR : STRING := "UNUSED";
PORT_B_ADDRESS_CLOCK : STRING := "UNUSED";
PORT_B_ADDRESS_WIDTH : NATURAL := 1;
PORT_B_BYTE_ENABLE_CLEAR : STRING := "UNUSED";
PORT_B_BYTE_ENABLE_CLOCK : STRING := "UNUSED";
PORT_B_BYTE_ENABLE_MASK_WIDTH : NATURAL := 1;
PORT_B_DATA_IN_CLEAR : STRING := "UNUSED";
PORT_B_DATA_IN_CLOCK : STRING := "UNUSED";
PORT_B_DATA_OUT_CLEAR : STRING := "UNUSED";
PORT_B_DATA_OUT_CLOCK : STRING := "none";
PORT_B_DATA_WIDTH : NATURAL := 1;
PORT_B_FIRST_ADDRESS : NATURAL := 0;
PORT_B_FIRST_BIT_NUMBER : NATURAL := 0;
PORT_B_LAST_ADDRESS : NATURAL := 0;
PORT_B_LOGICAL_RAM_DEPTH : NATURAL := 0;
PORT_B_LOGICAL_RAM_WIDTH : NATURAL := 0;
PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR : STRING := "UNUSED";
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK : STRING := "UNUSED";
POWER_UP_UNINITIALIZED : STRING := "false";
RAM_BLOCK_TYPE : STRING;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "cyclone_ram_block"
);
PORT
(
clk0 : IN STD_LOGIC;
clk1 : IN STD_LOGIC := '0';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
portaaddr : IN STD_LOGIC_VECTOR(PORT_A_ADDRESS_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(PORT_A_BYTE_ENABLE_MASK_WIDTH-1 DOWNTO 0) := (OTHERS => '1');
portadatain : IN STD_LOGIC_VECTOR(PORT_A_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
portadataout : OUT STD_LOGIC_VECTOR(PORT_A_DATA_WIDTH-1 DOWNTO 0);
portawe : IN STD_LOGIC := '0';
portbaddr : IN STD_LOGIC_VECTOR(PORT_B_ADDRESS_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
portbbyteenamasks : IN STD_LOGIC_VECTOR(PORT_B_BYTE_ENABLE_MASK_WIDTH-1 DOWNTO 0) := (OTHERS => '1');
portbdatain : IN STD_LOGIC_VECTOR(PORT_B_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
portbdataout : OUT STD_LOGIC_VECTOR(PORT_B_DATA_WIDTH-1 DOWNTO 0);
portbrewe : IN STD_LOGIC := '0'
);
END COMPONENT;
BEGIN
address_a_wire <= address_a;
address_b_wire <= address_b;
q_b <= ( wire_ram_block1a_9portbdataout(0) & wire_ram_block1a_8portbdataout(0) & wire_ram_block1a_7portbdataout(0) & wire_ram_block1a_6portbdataout(0) & wire_ram_block1a_5portbdataout(0) & wire_ram_block1a_4portbdataout(0) & wire_ram_block1a_3portbdataout(0) & wire_ram_block1a_2portbdataout(0) & wire_ram_block1a_1portbdataout(0) & wire_ram_block1a_0portbdataout(0));
wire_ram_block1a_portawe <= "1111111111";
wire_ram_block1a_0portaaddr <= ( address_a_wire(6 DOWNTO 0));
wire_ram_block1a_0portadatain(0) <= ( data_a(0));
wire_ram_block1a_0portbaddr <= ( address_b_wire(6 DOWNTO 0));
wire_ram_block1a_1portaaddr <= ( address_a_wire(6 DOWNTO 0));
wire_ram_block1a_1portadatain(0) <= ( data_a(1));
wire_ram_block1a_1portbaddr <= ( address_b_wire(6 DOWNTO 0));
wire_ram_block1a_2portaaddr <= ( address_a_wire(6 DOWNTO 0));
wire_ram_block1a_2portadatain(0) <= ( data_a(2));
wire_ram_block1a_2portbaddr <= ( address_b_wire(6 DOWNTO 0));
wire_ram_block1a_3portaaddr <= ( address_a_wire(6 DOWNTO 0));
wire_ram_block1a_3portadatain(0) <= ( data_a(3));
wire_ram_block1a_3portbaddr <= ( address_b_wire(6 DOWNTO 0));
wire_ram_block1a_4portaaddr <= ( address_a_wire(6 DOWNTO 0));
wire_ram_block1a_4portadatain(0) <= ( data_a(4));
wire_ram_block1a_4portbaddr <= ( address_b_wire(6 DOWNTO 0));
wire_ram_block1a_5portaaddr <= ( address_a_wire(6 DOWNTO 0));
wire_ram_block1a_5portadatain(0) <= ( data_a(5));
wire_ram_block1a_5portbaddr <= ( address_b_wire(6 DOWNTO 0));
wire_ram_block1a_6portaaddr <= ( address_a_wire(6 DOWNTO 0));
wire_ram_block1a_6portadatain(0) <= ( data_a(6));
wire_ram_block1a_6portbaddr <= ( address_b_wire(6 DOWNTO 0));
wire_ram_block1a_7portaaddr <= ( address_a_wire(6 DOWNTO 0));
wire_ram_block1a_7portadatain(0) <= ( data_a(7));
wire_ram_block1a_7portbaddr <= ( address_b_wire(6 DOWNTO 0));
wire_ram_block1a_8portaaddr <= ( address_a_wire(6 DOWNTO 0));
wire_ram_block1a_8portadatain(0) <= ( data_a(8));
wire_ram_block1a_8portbaddr <= ( address_b_wire(6 DOWNTO 0));
wire_ram_block1a_9portaaddr <= ( address_a_wire(6 DOWNTO 0));
wire_ram_block1a_9portadatain(0) <= ( data_a(9));
wire_ram_block1a_9portbaddr <= ( address_b_wire(6 DOWNTO 0));
ram_block1a_0 : cyclone_ram_block
GENERIC MAP (
CONNECTIVITY_CHECKING => "OFF",
LOGICAL_RAM_NAME => "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE => "dont_care",
OPERATION_MODE => "dual_port",
PORT_A_ADDRESS_CLEAR => "clear0",
PORT_A_ADDRESS_WIDTH => 7,
PORT_A_DATA_IN_CLEAR => "clear0",
PORT_A_DATA_WIDTH => 1,
PORT_A_FIRST_ADDRESS => 0,
PORT_A_FIRST_BIT_NUMBER => 0,
PORT_A_LAST_ADDRESS => 79,
PORT_A_LOGICAL_RAM_DEPTH => 80,
PORT_A_LOGICAL_RAM_WIDTH => 10,
PORT_A_WRITE_ENABLE_CLEAR => "clear0",
PORT_B_ADDRESS_CLEAR => "clear0",
PORT_B_ADDRESS_CLOCK => "clock1",
PORT_B_ADDRESS_WIDTH => 7,
PORT_B_DATA_OUT_CLEAR => "clear0",
PORT_B_DATA_OUT_CLOCK => "clock1",
PORT_B_DATA_WIDTH => 1,
PORT_B_FIRST_ADDRESS => 0,
PORT_B_FIRST_BIT_NUMBER => 0,
PORT_B_LAST_ADDRESS => 79,
PORT_B_LOGICAL_RAM_DEPTH => 80,
PORT_B_LOGICAL_RAM_WIDTH => 10,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR => "clear0",
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK => "clock1",
POWER_UP_UNINITIALIZED => "false",
RAM_BLOCK_TYPE => "auto"
)
PORT MAP (
clk0 => clock0,
clk1 => clock0,
clr0 => aclr0,
ena0 => wren_a,
portaaddr => wire_ram_block1a_0portaaddr,
portadatain => wire_ram_block1a_0portadatain,
portawe => wire_ram_block1a_portawe(0),
portbaddr => wire_ram_block1a_0portbaddr,
portbdataout => wire_ram_block1a_0portbdataout,
portbrewe => rden_b
);
ram_block1a_1 : cyclone_ram_block
GENERIC MAP (
CONNECTIVITY_CHECKING => "OFF",
LOGICAL_RAM_NAME => "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE => "dont_care",
OPERATION_MODE => "dual_port",
PORT_A_ADDRESS_CLEAR => "clear0",
PORT_A_ADDRESS_WIDTH => 7,
PORT_A_DATA_IN_CLEAR => "clear0",
PORT_A_DATA_WIDTH => 1,
PORT_A_FIRST_ADDRESS => 0,
PORT_A_FIRST_BIT_NUMBER => 1,
PORT_A_LAST_ADDRESS => 79,
PORT_A_LOGICAL_RAM_DEPTH => 80,
PORT_A_LOGICAL_RAM_WIDTH => 10,
PORT_A_WRITE_ENABLE_CLEAR => "clear0",
PORT_B_ADDRESS_CLEAR => "clear0",
PORT_B_ADDRESS_CLOCK => "clock1",
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