-- ================================================================================
-- File: CPRemove.vhd
-- Version: v1.0
-- Author: olivercamel
-- Date: May.26.2006
-- Description:
-- This CP remove module locates at OFDM Receiver of my design and suppose to
-- remove the Cyclic Prefix (16 words length) which is added by transmitter. Since
-- we assume that both two clocks of transmitter and receiver is strictly
-- accordant so that we did not do anything for synchronization which is usually
-- completed by a PLL. In my Receiver of OFDM procject, datas is sent by
-- transmitter and directly received by CPRemove part. CPRemove is composed by a
-- large FIFO which is used to buffer received datas and RAM which is used to
-- discard CP. The output data length is 64 words long, as well as the following
-- FFT parts. Two CP Remove is needed for Real and Imag parts respectively.
-- ================================================================================

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- ================================================================================

entity CPRemoveImag is
	port
	(
		-- clock input
		clk: in std_logic;
		-- asynchroism clear input
		aclr: in std_logic;
		-- 10 bit width input and output data ports
		inputData: in std_logic_vector (9 downto 0);
		outputData: out std_logic_vector (9 downto 0);
		-- simple ALTERA Atlantic interface ports
		sink_val: in std_logic;
		source_val: out std_logic;
		source_sop: out std_logic;
		source_eop: out std_logic;
		source_ena: in std_logic
	);
end CPRemoveImag;

-- ================================================================================

architecture structure of CPRemoveImag is

-- --------------------------------------------------------------------------------

-- declarations

-- fifo declaration
-- 256 words * 10 bits
component fifo_CPRemoveImag
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		rdreq		: IN STD_LOGIC ;
		wrreq		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
		usedw		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
end component;
-- connection signals
signal outputFIFO: std_logic_vector (9 downto 0);
signal readEnaFIFO: std_logic;
signal usedwFIFO: std_logic_vector (7 downto 0);
signal usedwIntFIFO: natural range 0 to 255;
-- delay signal
signal readEnaFIFO_d: std_logic;

-- RAM declaration
-- 10 bits * 80 words
component ram_CPRemoveImag
	PORT
	(
		aclr		: IN STD_LOGIC  := '0';
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		rdaddress		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
		rden		: IN STD_LOGIC  := '1';
		wraddress		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		q		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
end component;
-- connection signals
signal outputRAM: std_logic_vector (9 downto 0);
signal writeEnaRAM: std_logic;
signal readEnaRAM: std_logic;
signal writeAddRAM: std_logic_vector (6 downto 0);
signal readAddRAM: std_logic_vector (6 downto 0);
signal writeAddIntRAM: natural range 0 to 79;
signal readAddIntRAM: natural range 0 to 79;

-- FSM state declaration
type FSM_state is
	(
		Reset, CountFIFO, ReadFIFO, ReadRAM
	);
-- state signal
signal state: FSM_state;

-- interval interface signals
signal interval_source_val: std_logic;
signal interval_source_sop: std_logic;
signal interval_source_eop: std_logic;

-- delayed interface signals
signal interval_source_val_d: std_logic;
signal interval_source_sop_d: std_logic;
signal interval_source_eop_d: std_logic;

-- --------------------------------------------------------------------------------

begin

-- --------------------------------------------------------------------------------

-- fifo connection
u1: fifo_CPRemoveImag port map
	(
		aclr => aclr, clock => clk,
		data => inputData, wrreq => sink_val,
		q => outputFIFO, rdreq => readEnaFIFO,
		usedw => usedwFIFO
	);
	
-- convert to integer
usedwIntFIFO <= to_integer(unsigned(usedwFIFO));

-- delay readEnaFIFO
process(clk,readEnaFIFO)
begin
	if rising_edge(clk) then
		readEnaFIFO_d <= readEnaFIFO;
	end if;
end process;

-- RAM connection
u2: ram_CPRemoveImag port map
	(
		aclr => aclr, clock => clk,
		data => outputFIFO, q => outputRAM,
		rdaddress => readAddRAM, rden => readEnaRAM,
		wraddress => writeAddRAM, wren => readEnaFIFO_d
	);

-- convert to std_logic_vector
readAddRAM <= std_logic_vector(to_unsigned(readAddIntRAM,7));
writeAddRAM <= std_logic_vector(to_unsigned(writeAddIntRAM,7));

-- FSM state transfer process
process(aclr,clk,usedwIntFIFO,writeAddIntRAM,readAddIntRAM)
begin
	if aclr = '1' then
		state <= reset;
	else
		if rising_edge(clk) then
			case state is
				when Reset =>
					state <= CountFIFO;
				when CountFIFO =>
					if usedwIntFIFO >= 80 then
						state <= ReadFIFO;
					end if;
				when ReadFIFO =>
					if writeAddIntRAM = 78 then -- shut down earlier
						state <= ReadRAM;
					end if;
				when ReadRAM =>
					if readAddIntRAM = 79 then
						state <= CountFIFO;
					end if;
			end case;
		end if;
	end if;
end process;

-- state functional controlling read FIFO/RAM enable
process(state,source_ena)
begin
	case state is
		when Reset =>
			readEnaFIFO <= '0';
			readEnaRAM <= '0';
		when CountFIFO =>
			readEnaFIFO <= '0';
			readEnaRAM <= '0';
		when ReadFIFO =>
			readEnaFIFO <= '1';
			readEnaRAM <= '0';
		when ReadRAM =>
			readEnaFIFO <= '0';
			if source_ena = '1' then
				readEnaRAM <= '1';
			else
				readEnaRAM <= '0';
			end if;
	end case;
end process;

-- reading from FIFO process
process(aclr,clk,readEnaFIFO_d)
begin
	if aclr = '1' then
		writeAddIntRAM <= 0;
	else
		if rising_edge(clk) then
			if readEnaFIFO_d = '1' then
				if writeAddIntRAM = 79 then
					writeAddIntRAM <= 0;
				else
					writeAddIntRAM <= writeAddIntRAM + 1;
				end if;
			else
				writeAddIntRAM <= 0;
			end if;
		end if;
	end if;
end process;

-- RAM reading process
process(aclr,clk,readEnaRAM)
begin
	if aclr = '1' then
		readAddIntRAM <= 16;
	else
		if rising_edge(clk) then
			if readEnaRAM = '1' then
				if readAddIntRAM = 79 then
					readAddIntRAM <= 16;
				else
					readAddIntRAM <= readAddIntRAM + 1;
				end if;
			else
				readAddIntRAM <= 16;
			end if;
		end if;
	end if;
end process;

-- generate interface signals
process(clk,readEnaRAM,readAddIntRAM)
begin
	if rising_edge(clk) then
		if readEnaRAM = '1' then
			interval_source_val <= '1';
			if readAddIntRAM = 16 then
				interval_source_sop <= '1';
				interval_source_eop <= '0';
			elsif readAddIntRAM = 79 then
				interval_source_sop <= '0';
				interval_source_eop <= '1';
			else
				interval_source_sop <= '0';
				interval_source_eop <= '0';
			end if;
		else
			interval_source_val <= '0';
			interval_source_sop <= '0';
			interval_source_eop <= '0';
		end if;
	end if;
end process;

-- delay
process(clk,interval_source_val,interval_source_sop,interval_source_eop)
begin
	if rising_edge(clk) then
		interval_source_val_d <= interval_source_val;
		interval_source_sop_d <= interval_source_sop;
		interval_source_eop_d <= interval_source_eop;
	end if;
end process;

-- synchronize output using falling edge
process(clk,outputRAM,interval_source_val_d,
		interval_source_sop_d,interval_source_eop_d)
begin
	if falling_edge(clk) then -- using falling edge
		outputData <= outputRAM;
		source_val <= interval_source_val_d;
		source_sop <= interval_source_sop_d;
		source_eop <= interval_source_eop_d;
	end if;
end process;

-- --------------------------------------------------------------------------------

end structure;

-- ================================================================================