LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY watch IS
  PORT(clear:IN STD_LOGIC;
       s1,m1:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
       s2,m2:buffer std_logic_vector(2 downto 0);
       h:buffer std_logic_vector(4 downto 0));
END watch;
ARCHITECTURE behave OF watch IS
component clock
  port(clear:in std_logic;
       clk: out std_logic
       );
end component;

component second
  port(clk,clear:IN STD_LOGIC;
       cout1:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
       cout2:BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0)
       );
end component;

component minute
  PORT(clk,clear:IN STD_LOGIC;
       cout1:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
       cout2:BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0)
       );
end component;

component hour
  PORT(clk,clear:IN STD_LOGIC;
       cout:BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0)
       );
end component;
signal clk1,clr:std_logic;
signal gewei1,gewei2:std_logic_vector(3 downto 0);
signal shiwei1,shiwei2:std_logic_vector(2 downto 0);
signal xiaoshi:std_logic_vector(4 downto 0);
       
begin
clr<=clear;
s1<=gewei1(3 downto 0);
s2<=shiwei1(2 downto 0);
m1<=gewei2(3 downto 0);
m2<=shiwei2(2 downto 0);
h<=xiaoshi(4 downto 0);
dff1:clock port map(clr,clk1);
dff2:second port map(clk1,clr,gewei1(3 downto 0),shiwei1(2 downto 0));
dff3:minute port map(shiwei1(2),clr,gewei2(3 downto 0),shiwei2(2 downto 0));
dff4:hour port map(shiwei2(2),clr,xiaoshi(4 downto 0));
END behave;