; N/A   ; None         ; 8.413 ns   ; minute:dff3|cout1[3] ; m1[3] ; clk        ;
; N/A   ; None         ; 8.387 ns   ; minute:dff3|cout1[1] ; m1[1] ; clk        ;
; N/A   ; None         ; 8.266 ns   ; minute:dff3|cout2[2] ; m2[2] ; clk        ;
; N/A   ; None         ; 8.114 ns   ; minute:dff3|cout1[2] ; m1[2] ; clk        ;
; N/A   ; None         ; 8.104 ns   ; minute:dff3|cout1[0] ; m1[0] ; clk        ;
; N/A   ; None         ; 8.090 ns   ; minute:dff3|cout2[1] ; m2[1] ; clk        ;
; N/A   ; None         ; 8.084 ns   ; minute:dff3|cout2[0] ; m2[0] ; clk        ;
; N/A   ; None         ; 6.641 ns   ; second:dff2|cout1[0] ; s1[0] ; clk        ;
; N/A   ; None         ; 6.590 ns   ; second:dff2|cout2[0] ; s2[0] ; clk        ;
; N/A   ; None         ; 6.581 ns   ; second:dff2|cout2[1] ; s2[1] ; clk        ;
; N/A   ; None         ; 6.366 ns   ; second:dff2|cout1[3] ; s1[3] ; clk        ;
; N/A   ; None         ; 6.216 ns   ; second:dff2|cout2[2] ; s2[2] ; clk        ;
; N/A   ; None         ; 6.009 ns   ; second:dff2|cout1[1] ; s1[1] ; clk        ;
; N/A   ; None         ; 5.979 ns   ; second:dff2|cout1[2] ; s1[2] ; clk        ;
+-------+--------------+------------+----------------------+-------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 6.1 Build 201 11/27/2006 SJ Web Edition
    Info: Processing started: Thu May 17 11:10:42 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off watch -c watch --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "second:dff2|cout2[2]" as buffer
    Info: Detected ripple clock "minute:dff3|cout2[2]" as buffer
Info: Clock "clk" Internal fmax is restricted to 420.17 MHz between source register "hour:dff4|cout[0]" and destination register "hour:dff4|cout[3]"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.957 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y2_N15; Fanout = 4; REG Node = 'hour:dff4|cout[0]'
            Info: 2: + IC(0.307 ns) + CELL(0.485 ns) = 0.792 ns; Loc. = LCCOMB_X1_Y2_N14; Fanout = 2; COMB Node = 'hour:dff4|Add0~61'
            Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.863 ns; Loc. = LCCOMB_X1_Y2_N16; Fanout = 2; COMB Node = 'hour:dff4|Add0~63'
            Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 0.934 ns; Loc. = LCCOMB_X1_Y2_N18; Fanout = 2; COMB Node = 'hour:dff4|Add0~65'
            Info: 5: + IC(0.000 ns) + CELL(0.410 ns) = 1.344 ns; Loc. = LCCOMB_X1_Y2_N20; Fanout = 1; COMB Node = 'hour:dff4|Add0~66'
            Info: 6: + IC(0.254 ns) + CELL(0.275 ns) = 1.873 ns; Loc. = LCCOMB_X1_Y2_N0; Fanout = 1; COMB Node = 'hour:dff4|cout~83'
            Info: 7: + IC(0.000 ns) + CELL(0.084 ns) = 1.957 ns; Loc. = LCFF_X1_Y2_N1; Fanout = 4; REG Node = 'hour:dff4|cout[3]'
            Info: Total cell delay = 1.396 ns ( 71.33 % )
            Info: Total interconnect delay = 0.561 ns ( 28.67 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 6.549 ns
                Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.702 ns) + CELL(0.787 ns) = 2.590 ns; Loc. = LCFF_X27_Y7_N7; Fanout = 4; REG Node = 'second:dff2|cout2[2]'
                Info: 4: + IC(0.597 ns) + CELL(0.000 ns) = 3.187 ns; Loc. = CLKCTRL_G6; Fanout = 7; COMB Node = 'second:dff2|cout2[2]~clkctrl'
                Info: 5: + IC(0.689 ns) + CELL(0.787 ns) = 4.663 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 4; REG Node = 'minute:dff3|cout2[2]'
                Info: 6: + IC(0.641 ns) + CELL(0.000 ns) = 5.304 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'minute:dff3|cout2[2]~clkctrl'
                Info: 7: + IC(0.708 ns) + CELL(0.537 ns) = 6.549 ns; Loc. = LCFF_X1_Y2_N1; Fanout = 4; REG Node = 'hour:dff4|cout[3]'
                Info: Total cell delay = 3.090 ns ( 47.18 % )
                Info: Total interconnect delay = 3.459 ns ( 52.82 % )
            Info: - Longest clock path from clock "clk" to source register is 6.549 ns
                Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.702 ns) + CELL(0.787 ns) = 2.590 ns; Loc. = LCFF_X27_Y7_N7; Fanout = 4; REG Node = 'second:dff2|cout2[2]'
                Info: 4: + IC(0.597 ns) + CELL(0.000 ns) = 3.187 ns; Loc. = CLKCTRL_G6; Fanout = 7; COMB Node = 'second:dff2|cout2[2]~clkctrl'
                Info: 5: + IC(0.689 ns) + CELL(0.787 ns) = 4.663 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 4; REG Node = 'minute:dff3|cout2[2]'
                Info: 6: + IC(0.641 ns) + CELL(0.000 ns) = 5.304 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'minute:dff3|cout2[2]~clkctrl'
                Info: 7: + IC(0.708 ns) + CELL(0.537 ns) = 6.549 ns; Loc. = LCFF_X1_Y2_N15; Fanout = 4; REG Node = 'hour:dff4|cout[0]'
                Info: Total cell delay = 3.090 ns ( 47.18 % )
                Info: Total interconnect delay = 3.459 ns ( 52.82 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "clk" to destination pin "h[0]" through register "hour:dff4|cout[0]" is 10.110 ns
    Info: + Longest clock path from clock "clk" to source register is 6.549 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.702 ns) + CELL(0.787 ns) = 2.590 ns; Loc. = LCFF_X27_Y7_N7; Fanout = 4; REG Node = 'second:dff2|cout2[2]'
        Info: 4: + IC(0.597 ns) + CELL(0.000 ns) = 3.187 ns; Loc. = CLKCTRL_G6; Fanout = 7; COMB Node = 'second:dff2|cout2[2]~clkctrl'
        Info: 5: + IC(0.689 ns) + CELL(0.787 ns) = 4.663 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 4; REG Node = 'minute:dff3|cout2[2]'
        Info: 6: + IC(0.641 ns) + CELL(0.000 ns) = 5.304 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'minute:dff3|cout2[2]~clkctrl'
        Info: 7: + IC(0.708 ns) + CELL(0.537 ns) = 6.549 ns; Loc. = LCFF_X1_Y2_N15; Fanout = 4; REG Node = 'hour:dff4|cout[0]'
        Info: Total cell delay = 3.090 ns ( 47.18 % )
        Info: Total interconnect delay = 3.459 ns ( 52.82 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.311 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y2_N15; Fanout = 4; REG Node = 'hour:dff4|cout[0]'
        Info: 2: + IC(0.542 ns) + CELL(2.769 ns) = 3.311 ns; Loc. = PIN_L4; Fanout = 0; PIN Node = 'h[0]'
        Info: Total cell delay = 2.769 ns ( 83.63 % )
        Info: Total interconnect delay = 0.542 ns ( 16.37 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 100 megabytes of memory during processing
    Info: Processing ended: Thu May 17 11:10:43 2007
    Info: Elapsed time: 00:00:01