//------------------------------------------------------------------ 2 // Dual port memory (one read and one write port, same width) 3 //------------------------------------------------------------------ 4  5 module dp_ram #( 6         parameter adr_width = 11, 7         parameter dat_width = 8  8 ) ( 9         // read port a  10         input                       clk_a, 11         input      [adr_width-1:0]  adr_a, 12         output reg [dat_width-1:0]  dat_a, 13         // write port b 14         input                       clk_b, 15         input      [adr_width-1:0]  adr_b, 16         input      [dat_width-1:0]  dat_b, 17         input                       we_b 18 ); 19  20 parameter depth = (1 << adr_width); 21  22 // actual ram cells 23 reg [dat_width-1:0] ram [0:depth-1]; 24  25 //------------------------------------------------------------------ 26 // read port 27 //------------------------------------------------------------------ 28 always @(posedge clk_a) 29 begin 30         dat_a <= ram[adr_a]; 31 end 32  33 //------------------------------------------------------------------ 34 // write port 35 //------------------------------------------------------------------ 36 always @(posedge clk_b) 37 begin 38         if (we_b) begin 39                 ram[adr_b] <= dat_b; 40         end 41 end 42  43 endmodule