module DPLL_4count(fout2,idout,N,reset);output fout2;input  idout,reset;input[7:0] N;reg fout2;reg [7:0] out3;always @(posedge idout or  negedge reset)  begin     if (reset==0)         begin            out3<=0;fout2<=0;        end    else if (reset==1)       begin           if(out3==(N-1))            begin              out3<=0;fout2<=1;            end          else if(out3!=(N-1))              begin                out3<=out3+1;fout2<=0;             end      end  endendmodule