module JK(idclock,reset,j,k,q,qn);input idclock,reset,j,k;output q,qn;reg q,qn;always@(posedge idclock or negedge reset)begin   if(!reset) begin q<=1'b0 ;qn<='b1;end   else if(reset)   begin   case({j,k})     2'b00: begin q<=q; qn<=qn; end     2'b01: begin q<=1'b0;qn<='b1;end     2'b10: begin q<=1'b1;qn<=1'b0;end     2'b11: begin q<=~q;qn<=~qn; end   endcase   endendendmodule