module DPLL(fin,fout,kclock,reset,k,N,H);input fin,kclock,reset;input[3:0] k;input[7:0] N;input[7:0] H;output fout;reg fout;wire se,carry,borrow,idclock,idout,fout2;DPLL_xor      DPLL1(fin,fout,se);DPLL_2KCOUNT  DPLL2(se,reset,k,kclock,carry,borrow);DPLL_H        DPLL3(idclock,kclock,H,reset);DPLL_3count   DPLL4(idclock,carry,borrow,idout,reset);DPLL_4count   DPLL5(fout2,idout,N,reset);DPLL_two      DPLL6(fout2,fout,reset);endmodule