library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Fenpin16 is
    port(a,b:in std_logic;
         clk6:in std_logic;
         clock6:out std_logic);
end;
architecture one of Fenpin16 is
signal tmp:std_logic_vector(3 downto 0);
signal ddt:std_logic_vector(1 downto 0);
begin
process(clk6)
begin
if clk6'event and clk6='1' then
      tmp<=tmp+1;
end if;
ddt<=a&b;
case ddt is
when "00" => clock6<=tmp(3);
when "01" => clock6<=tmp(2);
when "10" => clock6<=tmp(1);
when "11" => clock6<=tmp(0);
when others =>null;
end case;
end process;
end;





library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
    port(clk0,reset0,updown:in std_logic;
                      cout:out std_logic;
     q:out std_logic_vector(3 downto 0 ));
end;
architecture behav of cnt10 is
signal  cq :std_logic_vector(3 downto 0);
begin
process(clk0,reset0,updown)
begin
if reset0='1' then cq<=(others=>'0');
elsif updown='0' then cq<=cq;
elsif clk0'event and clk0='1' then
if cq<"1001" then cq<=cq+1;
     else cq<=(others=>'0');
end if;
end if;
if cq="1001" then cout<='1';
    else cout<='0';
end if;
q<=cq;
end process;
end behav;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt16 is
    port(clk1,reset1,updownt,en:in std_logic;
sum:in std_logic_vector(3 downto 0 );
q1:out std_logic_vector(3 downto 0 );
yytt:out std_logic;
coutt:out std_logic);
end;
architecture behav of cnt16 is
begin
process(clk1,reset1,updownt)
variable aaa1 :std_logic_vector(3 downto 0);
begin
yytt<=updownt;
if reset1='1' then aaa1:=(others=>'0');
elsif updownt='0' then aaa1:=aaa1;
elsif clk1'event and clk1='1' then
if en='1' then  aaa1:=aaa1+sum;
end if;
end if;
if aaa1>"1001" then coutt<='1';aaa1:=aaa1-"1010";
else aaa1:=aaa1;coutt<='0';
end if;
q1<=aaa1;
end process;
end behav;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt99 is
port(clk2,reset2,updownp,load2:in std_logic;
d:in std_logic_vector(3 downto 0 );
enable:out std_logic;
y0,y1:out std_logic_vector(3 downto 0 );
ss,coutp:out std_logic);
end;
architecture behave of cnt99 is
signal  bb,kk :std_logic_vector(3 downto 0);
signal q99:std_logic;
signal yout:std_logic_vector(7 downto 0); begin
p1:   process(clk2,reset2,updownp)
begin
yout<=kk&bb;
if reset2='1' then bb<=(others=>'0');
elsif updownp='0' then bb<=bb;
elsif load2='1' then bb<=d;
elsif clk2'event and clk2='1' then
if bb<"1001" then bb<=bb+1; else bb<=(others=>'0');
end if; 
end if;
if bb="1001" then coutp<='1'; else coutp<='0';
end if;
y0<=bb;
end process;
p2:process(clk2,reset2,updownp)  begin
if reset2='1' then kk<=(others=>'0');
elsif updownp='0' then kk<=kk;
elsif clk2'event and clk2='1' then
if bb="1001" then 
if kk<"1001" then kk<=kk+1; else kk<=(others=>'0');
end if; end if; end if;
if yout>="0011" then enable<='1'; else enable<='0';
end if;
if kk="1001" and bb="1001" then q99<='1'; else q99<='0';
end if;
ss<=q99; y1<=kk;
end process;
end behave;