cnt_scan[10]_lut_out = cnt_scan[10] $ (!cnt_scan[10]_carry_eqn);
cnt_scan[10] = DFFEAS(cnt_scan[10]_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );

--A1L258 is cnt_scan[10]~125 at LC_X14_Y4_N4
--operation mode is arithmetic

A1L258 = CARRY(cnt_scan[10] & (!A1L256));


--cnt_scan[11] is cnt_scan[11] at LC_X14_Y4_N5
--operation mode is normal

cnt_scan[11]_carry_eqn = A1L258;
cnt_scan[11]_lut_out = cnt_scan[11] $ (cnt_scan[11]_carry_eqn);
cnt_scan[11] = DFFEAS(cnt_scan[11]_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--A1L332 is rtl~311 at LC_X14_Y4_N9
--operation mode is normal

A1L332 = cnt_scan[11] & cnt_scan[8] & cnt_scan[10] & cnt_scan[9];


--A1L333 is rtl~312 at LC_X13_Y4_N2
--operation mode is normal

A1L333 = A1L332 & A1L331 & A1L330;


--phase1 is phase1 at LC_X12_Y6_N8
--operation mode is normal

phase1_lut_out = phase1 # A1L328;
phase1 = DFFEAS(phase1_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , phase1, );


--main_state.10 is main_state.10 at LC_X11_Y8_N5
--operation mode is normal

main_state.10_lut_out = !A1L110 & (A1L11 & (wr_input) # !A1L11 & A1L111);
main_state.10 = DFFEAS(main_state.10_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--i2c_state.read_data is i2c_state.read_data at LC_X10_Y7_N7
--operation mode is normal

i2c_state.read_data_lut_out = A1L12 & (A1L275 # i2c_state.read_data & A1L13) # !A1L12 & (i2c_state.read_data & A1L13);
i2c_state.read_data = DFFEAS(i2c_state.read_data_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--A1L300 is readData_reg[0]~76 at LC_X11_Y8_N7
--operation mode is normal

A1L300 = main_state.10 & i2c_state.read_data;


--inner_state.start is inner_state.start at LC_X10_Y5_N3
--operation mode is normal

inner_state.start_lut_out = main_state.10 & !A1L17 & !A1L18 # !A1L14;
inner_state.start = DFFEAS(inner_state.start_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--inner_state.stop is inner_state.stop at LC_X10_Y5_N7
--operation mode is normal

inner_state.stop_lut_out = A1L19 & (A1L275 # A1L13 & inner_state.stop) # !A1L19 & A1L13 & inner_state.stop;
inner_state.stop = DFFEAS(inner_state.stop_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--A1L301 is readData_reg[0]~77 at LC_X10_Y5_N1
--operation mode is normal

A1L301 = !inner_state.stop & inner_state.start;


--inner_state.ack is inner_state.ack at LC_X11_Y5_N0
--operation mode is normal

inner_state.ack_lut_out = A1L24 # A1L22 # A1L29 & A1L30;
inner_state.ack = DFFEAS(inner_state.ack_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--A1L302 is readData_reg[0]~78 at LC_X11_Y8_N4
--operation mode is normal

A1L302 = A1L301 & phase1 & A1L300 & !inner_state.ack;


--clk_div[5] is clk_div[5] at LC_X10_Y4_N3
--operation mode is normal

clk_div[5]_lut_out = A1L121 & (clk_div[3] # !A1L335 # !A1L334);
clk_div[5] = DFFEAS(clk_div[5]_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--clk_div[2] is clk_div[2] at LC_X10_Y4_N2
--operation mode is normal

clk_div[2]_lut_out = A1L125 & (clk_div[3] # !A1L334 # !A1L335);
clk_div[2] = DFFEAS(clk_div[2]_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--A1L334 is rtl~313 at LC_X10_Y4_N7
--operation mode is normal

A1L334 = clk_div[5] & !clk_div[2] & cnt_scan[0] & !clk_div[7];


--clk_div[6] is clk_div[6] at LC_X10_Y4_N9
--operation mode is normal

clk_div[6]_lut_out = A1L128 & (clk_div[3] # !A1L334 # !A1L335);
clk_div[6] = DFFEAS(clk_div[6]_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--A1L335 is rtl~314 at LC_X10_Y4_N5
--operation mode is normal

A1L335 = clk_div[6] & !clk_div[4] & cnt_scan[1];


--A1L336 is rtl~315 at LC_X11_Y4_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

clk_div[4]_qfbk = clk_div[4];
A1L336 = !clk_div[6] & (clk_div[4]_qfbk & !cnt_scan[1]);

--clk_div[4] is clk_div[4] at LC_X11_Y4_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

clk_div[4] = DFFEAS(A1L336, GLOBAL(clk), GLOBAL(rst), , , A1L131, , , VCC);


--A1L1 is Select~18654 at LC_X16_Y7_N2
--operation mode is normal

A1L1 = !rd_input # !wr_input;


--cnt_delay[16] is cnt_delay[16] at LC_X13_Y8_N9
--operation mode is normal

cnt_delay[16]_lut_out = A1L141;
cnt_delay[16] = DFFEAS(cnt_delay[16]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--cnt_delay[15] is cnt_delay[15] at LC_X13_Y8_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

cnt_delay[15]_lut_out = GND;
cnt_delay[15] = DFFEAS(cnt_delay[15]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L144, , , VCC);


--cnt_delay[14] is cnt_delay[14] at LC_X13_Y8_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

cnt_delay[14]_lut_out = GND;
cnt_delay[14] = DFFEAS(cnt_delay[14]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L147, , , VCC);


--A1L337 is rtl~316 at LC_X13_Y8_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

cnt_delay[17]_qfbk = cnt_delay[17];
A1L337 = !cnt_delay[15] & !cnt_delay[14] & !cnt_delay[17]_qfbk & !cnt_delay[16];

--cnt_delay[17] is cnt_delay[17] at LC_X13_Y8_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

cnt_delay[17] = DFFEAS(A1L337, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L138, , , VCC);


--cnt_delay[9] is cnt_delay[9] at LC_X13_Y8_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

cnt_delay[9]_lut_out = GND;
cnt_delay[9] = DFFEAS(cnt_delay[9]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L152, , , VCC);


--cnt_delay[7] is cnt_delay[7] at LC_X12_Y7_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

cnt_delay[7]_lut_out = GND;
cnt_delay[7] = DFFEAS(cnt_delay[7]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L154, , , VCC);


--cnt_delay[6] is cnt_delay[6] at LC_X12_Y7_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

cnt_delay[6]_lut_out = GND;
cnt_delay[6] = DFFEAS(cnt_delay[6]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L157, , , VCC);


--A1L338 is rtl~317 at LC_X12_Y7_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

cnt_delay[11]_qfbk = cnt_delay[11];
A1L338 = !cnt_delay[6] & !cnt_delay[7] & !cnt_delay[11]_qfbk & !cnt_delay[9];

--cnt_delay[11] is cnt_delay[11] at LC_X12_Y7_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

cnt_delay[11] = DFFEAS(A1L338, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L149, , , VCC);


--cnt_delay[4] is cnt_delay[4] at LC_X12_Y7_N4
--operation mode is normal

cnt_delay[4]_lut_out = A1L163;
cnt_delay[4] = DFFEAS(cnt_delay[4]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--cnt_delay[3] is cnt_delay[3] at LC_X12_Y7_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

cnt_delay[3]_lut_out = GND;
cnt_delay[3] = DFFEAS(cnt_delay[3]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L165, , , VCC);


--cnt_delay[2] is cnt_delay[2] at LC_X12_Y7_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

cnt_delay[2]_lut_out = GND;
cnt_delay[2] = DFFEAS(cnt_delay[2]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L168, , , VCC);


--A1L339 is rtl~318 at LC_X12_Y7_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

cnt_delay[5]_qfbk = cnt_delay[5];
A1L339 = !cnt_delay[4] & !cnt_delay[3] & !cnt_delay[5]_qfbk & !cnt_delay[2];

--cnt_delay[5] is cnt_delay[5] at LC_X12_Y7_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

cnt_delay[5] = DFFEAS(A1L339, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L160, , , VCC);


--cnt_delay[0] is cnt_delay[0] at LC_X13_Y8_N5
--operation mode is normal

cnt_delay[0]_lut_out = A1L174 & (!A1L341 # !A1L343);
cnt_delay[0] = DFFEAS(cnt_delay[0]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--A1L340 is rtl~319 at LC_X13_Y8_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

cnt_delay[1]_qfbk = cnt_delay[1];
A1L340 = !cnt_delay[0] & (!cnt_delay[1]_qfbk);

--cnt_delay[1] is cnt_delay[1] at LC_X13_Y8_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

cnt_delay[1] = DFFEAS(A1L340, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, A1L171, , , VCC);


--A1L341 is rtl~320 at LC_X12_Y7_N8
--operation mode is normal

A1L341 = A1L339 & A1L338 & A1L340 & A1L337;


--cnt_delay[19] is cnt_delay[19] at LC_X15_Y7_N3
--operation mode is normal

cnt_delay[19]_lut_out = A1L177 & (!A1L341 # !A1L343);
cnt_delay[19] = DFFEAS(cnt_delay[19]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--cnt_delay[18] is cnt_delay[18] at LC_X15_Y7_N7
--operation mode is normal

cnt_delay[18]_lut_out = A1L178 & (!A1L341 # !A1L343);
cnt_delay[18] = DFFEAS(cnt_delay[18]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--cnt_delay[13] is cnt_delay[13] at LC_X15_Y7_N0
--operation mode is normal

cnt_delay[13]_lut_out = A1L181 & (!A1L341 # !A1L343);
cnt_delay[13] = DFFEAS(cnt_delay[13]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--cnt_delay[12] is cnt_delay[12] at LC_X15_Y7_N9
--operation mode is normal

cnt_delay[12]_lut_out = A1L184 & (!A1L341 # !A1L343);
cnt_delay[12] = DFFEAS(cnt_delay[12]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--A1L342 is rtl~321 at LC_X15_Y7_N5
--operation mode is normal

A1L342 = cnt_delay[19] & cnt_delay[13] & cnt_delay[18] & cnt_delay[12];


--cnt_delay[10] is cnt_delay[10] at LC_X15_Y7_N4
--operation mode is normal

cnt_delay[10]_lut_out = A1L187 & (!A1L341 # !A1L343);
cnt_delay[10] = DFFEAS(cnt_delay[10]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--cnt_delay[8] is cnt_delay[8] at LC_X15_Y7_N8
--operation mode is normal

cnt_delay[8]_lut_out = A1L190 & (!A1L341 # !A1L343);
cnt_delay[8] = DFFEAS(cnt_delay[8]_lut_out, GLOBAL(clk), GLOBAL(rst), , start_delaycnt, , , , );


--A1L343 is rtl~322 at LC_X15_Y7_N6
--operation mode is normal

A1L343 = cnt_delay[8] & (cnt_delay[10] & A1L342);


--A1L2 is Select~18655 at LC_X11_Y8_N8
--operation mode is normal

A1L2 = !main_state.00 & (!A1L341 # !A1L343 # !A1L1);


--main_state.01 is main_state.01 at LC_X11_Y7_N1
--operation mode is normal

main_state.01_lut_out = !A1L110 & (A1L11 & !wr_input # !A1L11 & (A1L34));
main_state.01 = DFFEAS(main_state.01_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--i2c_state.read_ini is i2c_state.read_ini at LC_X10_Y7_N0
--operation mode is normal

i2c_state.read_ini_lut_out = A1L18 & (main_state.10 # i2c_state.read_ini & A1L35) # !A1L18 & i2c_state.read_ini & (A1L35);
i2c_state.read_ini = DFFEAS(i2c_state.read_ini_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--A1L310 is reduce_nor~75 at LC_X10_Y7_N8
--operation mode is normal

A1L310 = i2c_state.read_data # i2c_state.read_ini;


--i2c_state.sendaddr is i2c_state.sendaddr at LC_X10_Y7_N1
--operation mode is normal

i2c_state.sendaddr_lut_out = A1L36 # !A1L16 & i2c_state.sendaddr & main_state.10;
i2c_state.sendaddr = DFFEAS(i2c_state.sendaddr_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--i2c_state.ini is i2c_state.ini at LC_X11_Y7_N0
--operation mode is normal

i2c_state.ini_lut_out = main_state.10 & (i2c_state.ini # !A1L37) # !main_state.10 & main_state.01 & (i2c_state.ini # !A1L37);
i2c_state.ini = DFFEAS(i2c_state.ini_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--A1L3 is Select~18656 at LC_X11_Y7_N4
--operation mode is normal

A1L3 = inner_state.ack & (i2c_state.read_ini # i2c_state.sendaddr # !i2c_state.ini);


--A1L4 is Select~18657 at LC_X10_Y8_N5
--operation mode is normal

A1L4 = A1L120 & (A1L300 & (inner_state.stop) # !A1L300 & phase1);


--i2c_state.write_data is i2c_state.write_data at LC_X10_Y7_N2
--operation mode is normal

i2c_state.write_data_lut_out = main_state.01 & (A1L18 # i2c_state.write_data) # !main_state.01 & (main_state.10 & i2c_state.write_data);
i2c_state.write_data = DFFEAS(i2c_state.write_data_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--A1L5 is Select~18658 at LC_X10_Y8_N7
--operation mode is normal

A1L5 = main_state.01 & (A1L310 # !inner_state.ack & i2c_state.write_data);


--A1L6 is Select~18659 at LC_X10_Y8_N6
--operation mode is normal

A1L6 = A1L4 # !A1L310 & A1L5 & inner_state.stop;


--phase3 is phase3 at LC_X10_Y6_N0
--operation mode is normal

phase3_lut_out = phase3 # A1L329;
phase3 = DFFEAS(phase3_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , phase3, );


--A1L7 is Select~18660 at LC_X11_Y8_N3
--operation mode is normal

A1L7 = main_state.10 & (!i2c_state.read_data) # !main_state.10 & (!inner_state.stop # !i2c_state.write_data);


--sda_buf is sda_buf at LC_X10_Y6_N6
--operation mode is normal

sda_buf_lut_out = !A1L46 & !A1L71 & !A1L65 # !A1L61;
sda_buf = DFFEAS(sda_buf_lut_out, GLOBAL(clk), GLOBAL(rst), , , , , , );


--A1L8 is Select~18661 at LC_X11_Y8_N9
--operation mode is normal

A1L8 = main_state.00 & (A1L7 & !sda_buf # !A1L7 & (phase3));


--A1L344 is rtl~323 at LC_X11_Y4_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

clk_div[7]_qfbk = clk_div[7];
A1L344 = !cnt_scan[0] & !clk_div[2] & !clk_div[7]_qfbk & !clk_div[5];

--clk_div[7] is clk_div[7] at LC_X11_Y4_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

clk_div[7] = DFFEAS(A1L344, GLOBAL(clk), GLOBAL(rst), , , A1L124, , , VCC);


--A1L328 is rtl~3 at LC_X11_Y4_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

clk_div[3]_qfbk = clk_div[3];
A1L328 = A1L344 & A1L336 & clk_div[3]_qfbk;

--clk_div[3] is clk_div[3] at LC_X11_Y4_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

clk_div[3] = DFFEAS(A1L328, GLOBAL(clk), GLOBAL(rst), , , A1L135, , , VCC);