?? i2c.tan.qmsg
字號:
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 12 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clk register inner_state.first register sda_buf 11.311 ns " "Info: Slack time is 11.311 ns for clock \"clk\" between source register \"inner_state.first\" and destination register \"sda_buf\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "91.65 MHz 10.911 ns " "Info: Fmax is 91.65 MHz (period= 10.911 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "21.513 ns + Largest register register " "Info: + Largest register to register requirement is 21.513 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "22.222 ns + " "Info: + Setup relationship between source and destination is 22.222 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 22.222 ns " "Info: + Latch edge is 22.222 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 22.222 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clk\" is 22.222 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 22.222 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clk\" is 22.222 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.343 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.343 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 79 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 79; CLK Node = 'clk'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "" { clk } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.293 ns) + CELL(0.918 ns) 7.343 ns sda_buf 2 REG LC_X10_Y6_N6 20 " "Info: 2: + IC(5.293 ns) + CELL(0.918 ns) = 7.343 ns; Loc. = LC_X10_Y6_N6; Fanout = 20; REG Node = 'sda_buf'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "6.211 ns" { clk sda_buf } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 29 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.92 % ) " "Info: Total cell delay = 2.050 ns ( 27.92 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.293 ns ( 72.08 % ) " "Info: Total interconnect delay = 5.293 ns ( 72.08 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "7.343 ns" { clk sda_buf } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.343 ns" { clk clk~combout sda_buf } { 0.000ns 0.000ns 5.293ns } { 0.000ns 1.132ns 0.918ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.343 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.343 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 79 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 79; CLK Node = 'clk'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "" { clk } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.293 ns) + CELL(0.918 ns) 7.343 ns inner_state.first 2 REG LC_X8_Y6_N0 6 " "Info: 2: + IC(5.293 ns) + CELL(0.918 ns) = 7.343 ns; Loc. = LC_X8_Y6_N0; Fanout = 6; REG Node = 'inner_state.first'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "6.211 ns" { clk inner_state.first } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 36 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.92 % ) " "Info: Total cell delay = 2.050 ns ( 27.92 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.293 ns ( 72.08 % ) " "Info: Total interconnect delay = 5.293 ns ( 72.08 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "7.343 ns" { clk inner_state.first } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.343 ns" { clk clk~combout inner_state.first } { 0.000ns 0.000ns 5.293ns } { 0.000ns 1.132ns 0.918ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "7.343 ns" { clk sda_buf } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.343 ns" { clk clk~combout sda_buf } { 0.000ns 0.000ns 5.293ns } { 0.000ns 1.132ns 0.918ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "7.343 ns" { clk inner_state.first } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.343 ns" { clk clk~combout inner_state.first } { 0.000ns 0.000ns 5.293ns } { 0.000ns 1.132ns 0.918ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" { } { { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 36 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns - " "Info: - Micro setup delay of destination is 0.333 ns" { } { { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 29 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "7.343 ns" { clk sda_buf } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.343 ns" { clk clk~combout sda_buf } { 0.000ns 0.000ns 5.293ns } { 0.000ns 1.132ns 0.918ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "7.343 ns" { clk inner_state.first } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.343 ns" { clk clk~combout inner_state.first } { 0.000ns 0.000ns 5.293ns } { 0.000ns 1.132ns 0.918ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.202 ns - Longest register register " "Info: - Longest register to register delay is 10.202 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inner_state.first 1 REG LC_X8_Y6_N0 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y6_N0; Fanout = 6; REG Node = 'inner_state.first'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "" { inner_state.first } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 36 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.740 ns) 1.671 ns Select~18705 2 COMB LC_X8_Y6_N2 4 " "Info: 2: + IC(0.931 ns) + CELL(0.740 ns) = 1.671 ns; Loc. = LC_X8_Y6_N2; Fanout = 4; COMB Node = 'Select~18705'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "1.671 ns" { inner_state.first Select~18705 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.155 ns) + CELL(0.740 ns) 3.566 ns Select~18713 3 COMB LC_X9_Y6_N1 1 " "Info: 3: + IC(1.155 ns) + CELL(0.740 ns) = 3.566 ns; Loc. = LC_X9_Y6_N1; Fanout = 1; COMB Node = 'Select~18713'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "1.895 ns" { Select~18705 Select~18713 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.212 ns) + CELL(0.511 ns) 5.289 ns Select~18715 4 COMB LC_X10_Y6_N4 2 " "Info: 4: + IC(1.212 ns) + CELL(0.511 ns) = 5.289 ns; Loc. = LC_X10_Y6_N4; Fanout = 2; COMB Node = 'Select~18715'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "1.723 ns" { Select~18713 Select~18715 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.740 ns) + CELL(0.914 ns) 6.943 ns Select~18716 5 COMB LC_X10_Y6_N2 1 " "Info: 5: + IC(0.740 ns) + CELL(0.914 ns) = 6.943 ns; Loc. = LC_X10_Y6_N2; Fanout = 1; COMB Node = 'Select~18716'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "1.654 ns" { Select~18715 Select~18716 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.740 ns) 8.413 ns Select~18724 6 COMB LC_X10_Y6_N9 1 " "Info: 6: + IC(0.730 ns) + CELL(0.740 ns) = 8.413 ns; Loc. = LC_X10_Y6_N9; Fanout = 1; COMB Node = 'Select~18724'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "1.470 ns" { Select~18716 Select~18724 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.728 ns) + CELL(1.061 ns) 10.202 ns sda_buf 7 REG LC_X10_Y6_N6 20 " "Info: 7: + IC(0.728 ns) + CELL(1.061 ns) = 10.202 ns; Loc. = LC_X10_Y6_N6; Fanout = 20; REG Node = 'sda_buf'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "1.789 ns" { Select~18724 sda_buf } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 29 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.706 ns ( 46.13 % ) " "Info: Total cell delay = 4.706 ns ( 46.13 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.496 ns ( 53.87 % ) " "Info: Total interconnect delay = 5.496 ns ( 53.87 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "10.202 ns" { inner_state.first Select~18705 Select~18713 Select~18715 Select~18716 Select~18724 sda_buf } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.202 ns" { inner_state.first Select~18705 Select~18713 Select~18715 Select~18716 Select~18724 sda_buf } { 0.000ns 0.931ns 1.155ns 1.212ns 0.740ns 0.730ns 0.728ns } { 0.000ns 0.740ns 0.740ns 0.511ns 0.914ns 0.740ns 1.061ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "7.343 ns" { clk sda_buf } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.343 ns" { clk clk~combout sda_buf } { 0.000ns 0.000ns 5.293ns } { 0.000ns 1.132ns 0.918ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "7.343 ns" { clk inner_state.first } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.343 ns" { clk clk~combout inner_state.first } { 0.000ns 0.000ns 5.293ns } { 0.000ns 1.132ns 0.918ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "10.202 ns" { inner_state.first Select~18705 Select~18713 Select~18715 Select~18716 Select~18724 sda_buf } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.202 ns" { inner_state.first Select~18705 Select~18713 Select~18715 Select~18716 Select~18724 sda_buf } { 0.000ns 0.931ns 1.155ns 1.212ns 0.740ns 0.730ns 0.728ns } { 0.000ns 0.740ns 0.740ns 0.511ns 0.914ns 0.740ns 1.061ns } } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clk register readData_reg\[0\] register readData_reg\[1\] 1.413 ns " "Info: Minimum slack time is 1.413 ns for clock \"clk\" between source register \"readData_reg\[0\]\" and destination register \"readData_reg\[1\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.258 ns + Shortest register register " "Info: + Shortest register to register delay is 1.258 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns readData_reg\[0\] 1 REG LC_X12_Y8_N0 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y8_N0; Fanout = 2; REG Node = 'readData_reg\[0\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "" { readData_reg[0] } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 116 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.978 ns) + CELL(0.280 ns) 1.258 ns readData_reg\[1\] 2 REG LC_X12_Y8_N6 2 " "Info: 2: + IC(0.978 ns) + CELL(0.280 ns) = 1.258 ns; Loc. = LC_X12_Y8_N6; Fanout = 2; REG Node = 'readData_reg\[1\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "1.258 ns" { readData_reg[0] readData_reg[1] } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 116 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.280 ns ( 22.26 % ) " "Info: Total cell delay = 0.280 ns ( 22.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.978 ns ( 77.74 % ) " "Info: Total interconnect delay = 0.978 ns ( 77.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "1.258 ns" { readData_reg[0] readData_reg[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.258 ns" { readData_reg[0] readData_reg[1] } { 0.000ns 0.978ns } { 0.000ns 0.280ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.155 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.155 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 22.222 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clk\" is 22.222 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 22.222 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clk\" is 22.222 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.343 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.343 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 79 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 79; CLK Node = 'clk'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "" { clk } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.293 ns) + CELL(0.918 ns) 7.343 ns readData_reg\[1\] 2 REG LC_X12_Y8_N6 2 " "Info: 2: + IC(5.293 ns) + CELL(0.918 ns) = 7.343 ns; Loc. = LC_X12_Y8_N6; Fanout = 2; REG Node = 'readData_reg\[1\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "6.211 ns" { clk readData_reg[1] } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 116 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.92 % ) " "Info: Total cell delay = 2.050 ns ( 27.92 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.293 ns ( 72.08 % ) " "Info: Total interconnect delay = 5.293 ns ( 72.08 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "7.343 ns" { clk readData_reg[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.343 ns" { clk clk~combout readData_reg[1] } { 0.000ns 0.000ns 5.293ns } { 0.000ns 1.132ns 0.918ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.343 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 7.343 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 79 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 79; CLK Node = 'clk'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "" { clk } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.293 ns) + CELL(0.918 ns) 7.343 ns readData_reg\[0\] 2 REG LC_X12_Y8_N0 2 " "Info: 2: + IC(5.293 ns) + CELL(0.918 ns) = 7.343 ns; Loc. = LC_X12_Y8_N0; Fanout = 2; REG Node = 'readData_reg\[0\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "6.211 ns" { clk readData_reg[0] } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 116 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.92 % ) " "Info: Total cell delay = 2.050 ns ( 27.92 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.293 ns ( 72.08 % ) " "Info: Total interconnect delay = 5.293 ns ( 72.08 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "7.343 ns" { clk readData_reg[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.343 ns" { clk clk~combout readData_reg[0] } { 0.000ns 0.000ns 5.293ns } { 0.000ns 1.132ns 0.918ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "7.343 ns" { clk readData_reg[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.343 ns" { clk clk~combout readData_reg[1] } { 0.000ns 0.000ns 5.293ns } { 0.000ns 1.132ns 0.918ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "7.343 ns" { clk readData_reg[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.343 ns" { clk clk~combout readData_reg[0] } { 0.000ns 0.000ns 5.293ns } { 0.000ns 1.132ns 0.918ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" { } { { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 116 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" { } { { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 116 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "7.343 ns" { clk readData_reg[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.343 ns" { clk clk~combout readData_reg[1] } { 0.000ns 0.000ns 5.293ns } { 0.000ns 1.132ns 0.918ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "7.343 ns" { clk readData_reg[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.343 ns" { clk clk~combout readData_reg[0] } { 0.000ns 0.000ns 5.293ns } { 0.000ns 1.132ns 0.918ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "1.258 ns" { readData_reg[0] readData_reg[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.258 ns" { readData_reg[0] readData_reg[1] } { 0.000ns 0.978ns } { 0.000ns 0.280ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "7.343 ns" { clk readData_reg[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.343 ns" { clk clk~combout readData_reg[1] } { 0.000ns 0.000ns 5.293ns } { 0.000ns 1.132ns 0.918ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "7.343 ns" { clk readData_reg[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.343 ns" { clk clk~combout readData_reg[0] } { 0.000ns 0.000ns 5.293ns } { 0.000ns 1.132ns 0.918ns } } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
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