|i2c
clk => cnt_delay[18].CLK
clk => cnt_delay[17].CLK
clk => cnt_delay[16].CLK
clk => cnt_delay[15].CLK
clk => cnt_delay[14].CLK
clk => cnt_delay[13].CLK
clk => cnt_delay[12].CLK
clk => cnt_delay[11].CLK
clk => cnt_delay[10].CLK
clk => cnt_delay[9].CLK
clk => cnt_delay[8].CLK
clk => cnt_delay[7].CLK
clk => cnt_delay[6].CLK
clk => cnt_delay[5].CLK
clk => cnt_delay[4].CLK
clk => cnt_delay[3].CLK
clk => cnt_delay[2].CLK
clk => cnt_delay[1].CLK
clk => cnt_delay[0].CLK
clk => clk_div[7].CLK
clk => clk_div[6].CLK
clk => clk_div[5].CLK
clk => clk_div[4].CLK
clk => clk_div[3].CLK
clk => clk_div[2].CLK
clk => clk_div[1].CLK
clk => clk_div[0].CLK
clk => phase0.CLK
clk => phase1.CLK
clk => phase2.CLK
clk => phase3.CLK
clk => start_delaycnt.CLK
clk => scl~reg0.CLK
clk => sda_buf.CLK
clk => link.CLK
clk => writeData_reg[7].CLK
clk => writeData_reg[6].CLK
clk => writeData_reg[5].CLK
clk => writeData_reg[4].CLK
clk => writeData_reg[3].CLK
clk => writeData_reg[2].CLK
clk => writeData_reg[1].CLK
clk => writeData_reg[0].CLK
clk => readData_reg[7].CLK
clk => readData_reg[6].CLK
clk => readData_reg[5].CLK
clk => readData_reg[4].CLK
clk => readData_reg[3].CLK
clk => readData_reg[2].CLK
clk => readData_reg[1].CLK
clk => readData_reg[0].CLK
clk => cnt_scan[11].CLK
clk => cnt_scan[10].CLK
clk => cnt_scan[9].CLK
clk => cnt_scan[8].CLK
clk => cnt_scan[7].CLK
clk => cnt_scan[6].CLK
clk => cnt_scan[5].CLK
clk => cnt_scan[4].CLK
clk => cnt_scan[3].CLK
clk => cnt_scan[2].CLK
clk => cnt_scan[1].CLK
clk => cnt_scan[0].CLK
clk => en[1]~reg0.CLK
clk => en[0]~reg0.CLK
clk => cnt_delay[19].CLK
clk => main_state~27.IN1
clk => i2c_state~20.IN1
clk => inner_state~46.IN1
rst => scl~reg0.PRESET
rst => sda_buf.PRESET
rst => link.ACLR
rst => writeData_reg[7].ACLR
rst => writeData_reg[6].ACLR
rst => writeData_reg[5].ACLR
rst => writeData_reg[4].ACLR
rst => writeData_reg[3].ACLR
rst => writeData_reg[2].PRESET
rst => writeData_reg[1].ACLR
rst => writeData_reg[0].PRESET
rst => readData_reg[7].ACLR
rst => readData_reg[6].ACLR
rst => readData_reg[5].ACLR
rst => readData_reg[4].ACLR
rst => readData_reg[3].ACLR
rst => readData_reg[2].ACLR
rst => readData_reg[1].ACLR
rst => readData_reg[0].ACLR
rst => cnt_scan[3].ACLR
rst => cnt_scan[4].ACLR
rst => cnt_scan[5].ACLR
rst => cnt_scan[6].ACLR
rst => cnt_scan[7].ACLR
rst => cnt_scan[8].ACLR
rst => cnt_scan[9].ACLR
rst => cnt_scan[10].ACLR
rst => cnt_scan[2].ACLR
rst => start_delaycnt.ACLR
rst => cnt_scan[1].ACLR
rst => cnt_scan[0].ACLR
rst => en[1]~reg0.PRESET
rst => en[0]~reg0.ACLR
rst => cnt_scan[11].ACLR
rst => cnt_delay[18].ACLR
rst => cnt_delay[17].ACLR
rst => cnt_delay[16].ACLR
rst => cnt_delay[15].ACLR
rst => cnt_delay[14].ACLR
rst => cnt_delay[13].ACLR
rst => cnt_delay[12].ACLR
rst => cnt_delay[11].ACLR
rst => cnt_delay[10].ACLR
rst => cnt_delay[9].ACLR
rst => cnt_delay[8].ACLR
rst => cnt_delay[7].ACLR
rst => cnt_delay[6].ACLR
rst => cnt_delay[5].ACLR
rst => cnt_delay[4].ACLR
rst => cnt_delay[3].ACLR
rst => cnt_delay[2].ACLR
rst => cnt_delay[1].ACLR
rst => cnt_delay[0].ACLR
rst => cnt_delay[19].ACLR
rst => clk_div[6].ACLR
rst => clk_div[5].ACLR
rst => clk_div[4].ACLR
rst => clk_div[3].ACLR
rst => clk_div[2].ACLR
rst => clk_div[1].ACLR
rst => clk_div[0].ACLR
rst => phase0.ACLR
rst => phase1.ACLR
rst => phase2.ACLR
rst => phase3.ACLR
rst => clk_div[7].ACLR
rst => main_state~28.IN1
rst => i2c_state~21.IN1
rst => inner_state~47.IN1
data_in[0] => writeData_reg[0].DATAIN
data_in[1] => writeData_reg[1].DATAIN
data_in[2] => writeData_reg[2].DATAIN
data_in[3] => writeData_reg[3].DATAIN
scl <= scl~reg0.DB_MAX_OUTPUT_PORT_TYPE
sda <= sda~0
wr_input => main_state~3.OUTPUTSELECT
wr_input => main_state~4.OUTPUTSELECT
wr_input => main_state~5.OUTPUTSELECT
wr_input => always2~0.IN1
rd_input => main_state~0.OUTPUTSELECT
rd_input => main_state~1.OUTPUTSELECT
rd_input => main_state~2.OUTPUTSELECT
rd_input => always2~0.IN0
lowbit <= <GND>
en[0] <= en[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
en[1] <= en[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
seg_data[0] <= <VCC>
seg_data[1] <= reduce_or~9.DB_MAX_OUTPUT_PORT_TYPE
seg_data[2] <= reduce_or~8.DB_MAX_OUTPUT_PORT_TYPE
seg_data[3] <= reduce_or~7.DB_MAX_OUTPUT_PORT_TYPE
seg_data[4] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
seg_data[5] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
seg_data[6] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
seg_data[7] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE