library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY vote7 is
PORT (men:IN std_logic_vector(6 downto 0);
stop:buffer std_logic);
END vote7;
ARCHITECTURE behave OF vote7 IS
BEGIN
PROCESS(men)
variable temp:std_logic_vector(2 downto 0);
BEGIN
temp:="000";
for i in 0 to 6 loop
 if(men(i)='1')then
 temp:=temp+1;
else temp:=temp+0;
end if;
end loop;
stop<=temp(2);
END PROCESS;
 END behave;